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mb95710m series mb95770m series new 8fx 8-bit microcontrollers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-09307 rev. *d revised september 29, 2017 the mb95710m/770m series is a series of general-purpose, single -chip microcontrollers. in addition to a compact instruction set , the microcontrollers of this series contain a variety of peripheral resources. features f 2 mc-8fx cpu core ? instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test bran ch instructions ? bit manipulation instructions, etc. clock ? selectable main clock source ? main oscillation clock (up to 16.25 mhz, maximum ma- chine clock frequency: 8.125 mhz) ? external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) ? main cr clock (4 mhz 2%) ? main cr pll clock - the main cr pll clock frequency becomes 8 mhz 2% when the pll multiplication rate is 2. - the main cr pll clock frequency becomes 10 mhz 2% when the pll multiplication rate is 2.5. - the main cr pll clock frequency becomes 12 mhz 2% when the pll multiplication rate is 3. - the main cr pll clock frequency becomes 16 mhz 2% when the pll multiplication rate is 4. ?main pll clock (up to 16.25 mhz, maximum machine clock frequency: 16.25 mhz) ? selectable subclock source ? suboscillation clock (32.768 khz) ? external clock (32.768 khz) ? sub-cr clock (typ: 100 khz, min: 50 khz, max: 150 khz) timer ? 8/16-bit composite timer 2 channels ? 8/16-bit ppg 2 channels ? 16-bit reload timer 1 channel ? event counter 1 channel ? time-base timer 1 channel ? watch counter 1 channel ? watch prescaler 1 channel uart/sio 3 channels ? full duplex double buffer ? capable of clock asynchronous (uart) serial data transfer and clock synchronous (sio) serial data transfer i 2 c bus interface 1 channel ? built-in wake-up function external interrupt 8 channels ? interrupt by edge detection (r ising edge, falling edge, and both edges can be selected) ? can be used to wake up the device from different low power consumption (standby) modes 8/12-bit a/d converter 8 channels ? 8-bit or 12-bit resolution can be selected. lcd controller (lcdc) ? on mb95f714j/f714m/f716j/f716m/f718j/f718m, lcd output can be selected from 40 seg 4 com and 36 seg 8 com. ? on mb95f774j/f774m/f776j/f776m/f778j/f778m, lcd output can be selected from 32 seg 4 com and 28 seg 8 com. ? internal divider resistor whose resistance value can be se- lected from 10 k or 100 k through software ? interrupt in sync with the lcd module frame frequency ? blinking function ? inverted display function low power consumption (standby) modes ? there are four standby modes as follows: ? stop mode ? sleep mode ?watch mode ? time-base timer mode i/o port ? mb95f714j/f716j/f718j (number of i/o ports: 75) ? general-purpose i/o ports (cmos i/o): 71 ? general-purpose i/o ports (n-ch open drain): 4 ? mb95f714m/f716m/f718m (num ber of i/o ports: 74) ? general-purpose i/o ports (cmos i/o): 71 ? general-purpose i/o ports (n-ch open drain): 3 ? mb95f774j/f776j/f778j (number of i/o ports: 59) ? general-purpose i/o ports (cmos i/o): 55 ? general-purpose i/o ports (n-ch open drain): 4 ? mb95f774m/f776m/f778m (num ber of i/o ports: 58) ? general-purpose i/o ports (cmos i/o): 55 ? general-purpose i/o ports (n-ch open drain): 3 on-chip debug ? 1-wire serial control ? serial writing supported (asynchronous mode) hardware/software watchdog timer ? built-in hardware watchdog timer ? built-in software watchdog timer power-on reset ? a power-on reset is generated when the power is switched on.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 2 of 172 low-voltage detection (lvd) circuit (only available on mb95f714j/f716j/f718j/f774j/f776j/f778j) ? built-in low-voltage detection function comparator 1 channel clock supervisor counter ? built-in clock supervisor counter dual operation flash memory ? the program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simul- taneously. flash memory security function ? protects the content of the flash memory.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 3 of 172 contents features............................................................................. 1 1. product line-up ............................................................ 4 1.1 mb95710m series................................................. 4 1.2 mb95770m series................................................. 7 2. packages and corresponding products.................... 9 3. differences among pr oducts and notes on product selection ........................................................... 10 4. pin assignment .......................................................... 11 5. pin functions (mb95710m series) ............................ 13 6. pin functions (mb95770m series) ............................ 19 7. i/o circuit type ........................................................... 24 8. handling precaution s............ .............. .............. ......... 28 8.1 precautions for product design........................... 28 8.2 precautions for package mounting ..................... 29 8.3 precautions for use environment........................ 30 9. notes on device handling......................................... 31 10. pin connection ......................................................... 31 11. block diagram (mb95710m series)......................... 33 12. block diagram (mb95770m series)......................... 34 13. cpu core................................................................... 35 14. memory space .......................................................... 36 15. areas for specific applicat ions ...... .............. ......... 38 16. i/o map (mb95710m series)..................................... 39 17. i/o map (mb95770m series)..................................... 45 18. i/o ports (mb95710m series). .............. .............. ...... 51 18.1 port 0................................................................. 52 18.2 port 1................................................................. 56 18.3 port 2................................................................. 61 18.4 port 4................................................................. 64 18.5 port 5................................................................. 66 18.6 port 6................................................................. 69 18.7 port 9................................................................. 72 18.8 port a ................................................................ 74 18.9 port b ................................................................ 77 18.10 port c .............................................................. 79 18.11 port e .............................................................. 82 18.12 port f............................................................... 85 18.13 port g .............................................................. 87 19. i/o ports (mb95770m series)................................... 90 19.1 port 0................................................................. 91 19.2 port 1................................................................. 95 19.3 port 2............................................................... 100 19.4 port 6............................................................... 103 19.5 port 9............................................................... 106 19.6 port a .............................................................. 108 19.7 port b .............................................................. 111 19.8 port c .............................................................. 113 19.9 port e .............................................................. 116 19.10 port f............................................................. 119 19.11 port g ............................................................ 121 20. interrupt source table ........................................... 124 21. pin states in each mode ........................................ 125 22. electrical characteristics... .................................... 131 22.1 absolute maximum rating s............................. 131 22.2 recommended operating conditions ............. 133 22.3 dc characteristics ......... ................................. 134 22.4 ac characteristics.......... ................................. 139 22.5 a/d converter............. .................................... 155 22.6 flash memory program/erase characteristics 159 23. sample characteristics...... .................................... 160 24. mask options .......................................................... 166 25. ordering information.............................................. 167 26. package dimension. .............. .............. .............. ..... 168 document history page .............. ................................. 171 sales, solutions, and legal information .................... 172
mb95710m series mb95770m series document number: 002-09307 rev. *d page 4 of 172 1. product line-up 1.1 mb95710m series part number parameter mb95f714j mb95f716j mb95f718j mb95f714m mb95f716m mb95f718m type flash memory product clock supervisor counter it supervises the main clock osc illation and the subclock oscillation. flash memory capacity 20 kbyte 36 kbyte 60 kbyte 20 kbyte 36 kbyte 60 kbyte ram capacity 512 bytes 1 kbyte 2 kbyte 512 bytes 1 kbyte 2 kbyte power-on reset yes low-voltage detection reset yes no reset input selected through software with dedicated reset input cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o port : 75 ?cmos i/o :71 ? n-ch open drain : 4 ? i/o port : 74 ?cmos i/o :71 ? n-ch open drain : 3 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be us ed as the source clock of the software watchdog timer. wild register it can be used to replace 3 bytes of data. 8/12-bit a/d converter 8 channels 8-bit or 12-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an ?8-bit timer 2 channels? or a ?16-bit timer 1 channel?. ? it has the following functions: interval timer func tion, pwc function, pwm fu nction and input capture function. ? count clock: it can be selected from intern al clocks (seven types) and external clocks. ? it can output square wave. external interrupt 8 channels ? interrupt by edge detection (the rising edge, falling edge, a nd both edges can be selected.) ? it can be used to wake up the device from different standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode).
mb95710m series mb95770m series document number: 002-09307 rev. *d page 5 of 172 uart/sio 3 channels ? data transfer with uart/sio is enabled. ? it has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. ? it uses the nrz type transfer format. ? lsb-first data transfer and msb-first data transfer are available to use. ? both clock asynchronous (uart) serial data transfe r and clock synchronous (sio) serial data transfer are enabled. i 2 c bus interface 1 channel ? master/slave transmission and reception ? it has the following functions: bus error function, arbitration function, trans mission direction detection function, wake-up function, and functions of generating and dete cting repeated start conditions. 8/16-bit ppg 2 channels ? each channel can be used as an ?8-bit timer 2 channels? or a ?16-bit timer 1 channel?. ? the counter operating clock can be selected from eight clock sources. 16-bit reload timer 1 channel ? two clock modes and two counter operating modes are available to use. ? it can output square wave. ? count clock: it can be selected from intern al clocks (seven types) and external clocks. ? two counter operating modes: reload mode and one-shot mode event counter ? the event counter function is implemented by conf iguring the 16-bit reload timer and 8/16-bit com- posite timer ch. 1. ? when the event counter function is used, the 16-bi t reload timer and 8/16-bit composite timer ch. 1 become unavailable. lcd controller (lcdc) ? com output: 4 or 8 (max) (selectable) ? seg output: 36 or 40 (max) (selectable) - if the number of com outputs is 4, the ma ximum number of seg outputs is 40, and the maximum number of pixels that can be displayed 160 (4 40). - if the number of com outputs is 8, the ma ximum number of seg outputs is 36, and the maximum number of pixels that can be displayed 288 (8 36). ? lcd drive power supply (bias) pins: 5 (max) ? duty lcd mode ? lcd standby mode ? blinking function ? internal divider resistor whose resistance value can be selected from 10 k or 100 k through software ? interrupt in sync with the lcd module frame frequency ? inverted display function watch counter ? count clock: four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) ? the counter value can be selected from 0 to 63. (the watch counter can count for one minute when the clock source is on e second and the counter value is set to 60.) watch prescaler eight different time intervals can be selected. comparator 1 channel part number parameter mb95f714j mb95f716j mb95f718j mb95f714m mb95f716m mb95f718m
mb95710m series mb95770m series document number: 002-09307 rev. *d page 6 of 172 flash memory ? it supports automatic programming (embe dded algorithm), and program/erase/erase- suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode there are four standby modes as follows: ? stop mode ? sleep mode ?watch mode ? time-base timer mode package lqh080 part number parameter mb95f714j mb95f716j mb95f718j mb95f714m mb95f716m mb95f718m number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
mb95710m series mb95770m series document number: 002-09307 rev. *d page 7 of 172 1.2 mb95770m series part number parameter mb95f774j mb95f776j mb95f778j mb95f774m mb95f776m mb95f778m type flash memory product clock supervisor counter it supervises the main clock osc illation and the subclock oscillation. flash memory capacity 20 kbyte 36 kbyte 60 kbyte 20 kbyte 36 kbyte 60 kbyte ram capacity 512 bytes 1 kbyte 2 kbyte 512 bytes 1 kbyte 2 kbyte power-on reset yes low-voltage detection reset yes no reset input selected through software dedicated cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o port : 59 ?cmos i/o :55 ? n-ch open drain : 4 ? i/o port : 58 ?cmos i/o :55 ? n-ch open drain : 3 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be us ed as the source clock of the software watchdog timer. wild register it can be used to replace 3 bytes of data. 8/12-bit a/d converter 8 channels 8-bit or 12-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an ?8-bit timer 2 channels? or a ?16-bit timer 1 channel?. ? it has the following functions: interval timer func tion, pwc function, pwm f unction and input capture function. ? count clock: it can be selected from intern al clocks (seven types) and external clocks. ? it can output square wave. external interrupt 8 channels ? interrupt by edge detection (the rising edge, falling edge, a nd both edges can be selected.) ? it can be used to wake up the device from different standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode).
mb95710m series mb95770m series document number: 002-09307 rev. *d page 8 of 172 uart/sio 3 channels ? data transfer with uart/sio is enabled. ? it has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. ? it uses the nrz type transfer format. ? lsb-first data transfer and msb-first data transfer are available to use. ? both clock asynchronous (uart) serial data transf er and clock synchronous (s io) serial data transfer are enabled. i 2 c bus interface 1 channel ? master/slave transmission and reception ? it has the following functions: bus error function, arbitration function, transmission direction detection function, wake-up function, and functions of generating and dete cting repeated start conditions. 8/16-bit ppg 2 channels ? each channel can be used as an ?8-bit timer 2 channels? or a ?16-bit timer 1 channel?. ? the counter operating clock can be selected from eight clock sources. 16-bit reload timer 1 channel ? two clock modes and two counter operating modes are available to use. ? it can output square wave. ? count clock: it can be selected from intern al clocks (seven types) and external clocks. ? two counter operating modes: reload mode and one-shot mode event counter ? the event counter function is implemented by configuring the 16-bit reload timer and 8/16-bit com- posite timer ch. 1. ? when the event counter function is used, the 16-b it reload timer and 8/16-bit composite timer ch. 1 become unavailable. lcd controller (lcdc) ? com output: 4 or 8 (max) (selectable) ? seg output: 28 or 32 (max) (selectable) - if the number of com outputs is 4, the ma ximum number of seg outputs is 32, and the maximum number of pixels that can be displayed 128 (4 32). - if the number of com outputs is 8, the ma ximum number of seg outputs is 28, and the maximum number of pixels that can be displayed 224 (8 28). ? lcd drive power supply (bias) pins: 4 (max) ? duty lcd mode ? lcd standby mode ? blinking function ? internal divider resistor whose resist ance value can be selected from 10 k or 100 k through software ? interrupt in sync with the lcd module frame frequency ? inverted display function watch counter ? count clock: four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) ? the counter value can be selected from 0 to 63 . (the watch counter can count for one minute when the clock source is on e second and the counter value is set to 60.) watch prescaler eight different time intervals can be selected. comparator 1 channel part number parameter mb95f774j mb95f776j mb95f778j mb95f774m mb95f776m mb95f778m
mb95710m series mb95770m series document number: 002-09307 rev. *d page 9 of 172 2. packages and corresponding products : available flash memory ? it supports automatic programming (embedd ed algorithm), and program/erase/erase- suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode there are four standby modes as follows: ? stop mode ? sleep mode ?watch mode ? time-base timer mode package lqd064 lqg064 part number package mb95f714j mb95f716j mb95f718j mb95f714m mb95f716m mb95f718m lqh080 ????? part number package mb95f774j mb95f776j mb95f778j mb95f774m mb95f776m mb95f778m lqd064 ????? lqg064 ????? part number parameter mb95f774j mb95f776j mb95f778j mb95f774m mb95f776m mb95f778m number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
mb95710m series mb95770m series document number: 002-09307 rev. *d page 10 of 172 3. differences am ong products and notes on product selection ? current consumption when using the on-chip debug function, take account of the current consumption of flash memory program/erase. for details of current consumption, see ?electrical characteristics?. ? package for details of information on each package, see ?package s and corresponding products ? and ?package dimension?. ? operating voltage the operating voltage varies, depending on whet her the on-chip debug function is used or not. for details of operating voltage, see ?electrical characteristics?. ? on-chip debug function the on-chip debug function requires that v cc , v ss and one serial wire be connected to an evaluation tool. for details of the connection method, refer to ?chapter 26 example of serial programming conn ection? in ?new 8fx mb95710m/770m series hardware manual?.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 11 of 172 4. pin assignment p07/int07/an07/seg30 p06/int06/an06/seg31 p05/int05/an05/seg32/uck1 p04/int04/an04/seg33/ui1 p03/int03/an03/seg34/uo1 p02/int02/an02/seg35/uck2 p01/int01/an01/seg36/ui2 p00/int00/an00/uo2 p16/ppg10 p15/ppg11 p14/uck0 (top view) lqfp80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 19 18 17 16 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 avcc p12/dbg p11/uo0 p10/ui0 p53/to0 p52/ti0/to00 p51/ec0 p50/to01 p13/adtg p22/scl p21/ppg01/cmp0_p p20/ppg00/cmp0_n p90/v4 p91/v3 p92/v2 p93/v1 p94/v0 pb2/seg37 pb3/seg38 pb4/seg39 p23/sda pa1/com1 pa2/com2 pa3/com3 pa4/com4 pa5/com5 pa6/com6 pa7/com7 pa0/com0 pc7/seg09 pc6/seg08 pc5/seg07 pc4/seg06 pc3/seg05 pc2/seg04 pc1/seg03 pc0/seg02 pb1/seg01 pb0/seg00 p17/cmp0_o 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 41 42 43 44 45 p60/seg10 vcc pg1/x0a pg2/x1a c pf0/x0 pf1/x1 vss pf2/rst pe7/seg29/ec1 pe6/seg28/to10 pe5/seg27/to11 pe4/seg26 pe3/seg25 pe2/seg24 pe1/seg23 pe0/seg22 p40/seg21 p41/seg20 p42/seg19 avss p67/seg17 p66/seg16 p65/seg15 p64/seg14 p63/seg13 p62/seg12 p61/seg11 p43/seg18 (lqh080) mb95710m series
mb95710m series mb95770m series document number: 002-09307 rev. *d page 12 of 172 p07/int07/an07/seg22 p06/int06/an06/seg23 p05/int05/an05/seg24/uck1 p04/int04/an04/seg25/ui1 p03/int03/an03/seg26/uo1 p02/int02/an02/seg27/uck2 p01/int01/an01/seg28/to00/ui2 p00/int00/an00/seg29/uo2 p16/seg30/ppg10 p15/seg31/ppg11 p14/uck0/ec0/ti0 (top view) lqfp64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avcc p12/dbg p11/uo0 p10/ui0/to0 p13/adtg/to01 p22/scl p21/ppg01/cmp0_p p20/ppg00/cmp0_n p90/v4 p91/v3 p92/v2 p93/v1 p23/sda pa1/com1 pa2/com2 pa3/com3 pa4/com4 pa5/com5 pa6/com6 pa7/com7 pa0/com0 p60/seg06 pc3/seg05 pc2/seg04 pc1/seg03 pc0/seg02 pb1/seg01 pb0/seg00 p17/cmp0_o 48 47 46 45 44 43 42 41 40 39 38 33 34 35 36 37 vcc pg1/x0a pg2/x1a c pf0/x0 pf1/x1 vss pf2/rst pe7/seg21/ec1 pe6/seg20/to10 pe5/seg19/to11 pe4/seg18 pe3/seg17 pe2/seg16 pe1/seg15 pe0/seg14 avss p67/seg13 p66/seg12 p65/seg11 p64/seg10 p63/seg09 p62/seg08 p61/seg07 (lqd064) (lqg064) mb95770m series
mb95710m series mb95770m series document number: 002-09307 rev. *d page 13 of 172 5. pin functions (mb95710m series) pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3 1av cc ? power supply pin for 8/12-bit a/d converter and comparator ???? 2 p07 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int07 external interrupt input pin an07 8/12-bit a/d conver ter analog input pin seg30 lcdc seg30 output pin 3 p06 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int06 external interrupt input pin an06 8/12-bit a/d conver ter analog input pin seg31 lcdc seg31 output pin 4 p05 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int05 external interrupt input pin an05 8/12-bit a/d conver ter analog input pin seg32 lcdc seg32 output pin uck1 uart/sio ch. 1 clock i/o pin 5 p04 v general-purpose i/o port cmos/ analog cmos/ lcd ?? int04 external interrupt input pin an04 8/12-bit a/d conver ter analog input pin seg33 lcdc seg33 output pin ui1 uart/sio ch. 1 data input pin 6 p03 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int03 external interrupt input pin an03 8/12-bit a/d conver ter analog input pin seg34 lcdc seg34 output pin uo1 uart/sio ch. 1 data output pin 7 p02 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int02 external interrupt input pin an02 8/12-bit a/d conver ter analog input pin seg35 lcdc seg35 output pin uck2 uart/sio ch. 2 clock i/o pin 8 p01 v general-purpose i/o port cmos/ analog cmos/ lcd ?? int01 external interrupt input pin an01 8/12-bit a/d conver ter analog input pin seg36 lcdc seg36 output pin ui2 uart/sio ch. 2 data input pin
mb95710m series mb95770m series document number: 002-09307 rev. *d page 14 of 172 9 p00 w general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int00 external interrupt input pin an00 8/12-bit a/d conver ter analog input pin uo2 uart/sio ch. 2 data output pin 10 p16 y general-purpose i/o port hysteresis cmos ?? ppg10 8/16-bit ppg ch. 1 output pin 11 p15 y general-purpose i/o port hysteresis cmos ?? ppg11 8/16-bit ppg ch. 1 output pin 12 p14 h general-purpose i/o port hysteresis cmos ? uck0 uart/sio ch. 0 clock i/o pin 13 p13 h general-purpose i/o port hysteresis cmos ? adtg 8/12-bit a/d converter trigger input pin 14 p12 d general-purpose i/o port hysteresis cmos ? dbg dbg input pin 15 p11 h general-purpose i/o port hysteresis cmos ? uo0 uart/sio ch. 0 data output pin 16 p10 g general-purpose i/o port cmos cmos ? ui0 uart/sio ch. 0 data input pin 17 p53 h general-purpose i/o port hysteresis cmos ? to0 16-bit reload timer ch. 0 output pin 18 p52 h general-purpose i/o port hysteresis cmos ? ti0 16-bit reload timer ch. 0 input pin to00 8/16-bit composite timer ch. 0 output pin 19 p51 h general-purpose i/o port hysteresis cmos ? ec0 8/16-bit composite timer ch. 0 clock input pin 20 p50 h general-purpose i/o port hysteresis cmos ? to01 8/16-bit composite timer ch. 0 output pin 21 p23 i general-purpose i/o port cmos cmos ? sda i 2 c bus interface ch. 0 data i/o pin 22 p22 i general-purpose i/o port cmos cmos ? scl i 2 c bus interface ch. 0 clock i/o pin 23 p21 t general-purpose i/o port hysteresis/ analog cmos ? ppg01 8/16-bit ppg ch. 0 output pin cmp0_p comparator ch. 0 non-inverting analog input (positive input) pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 15 of 172 24 p20 t general-purpose i/o port hysteresis/ analog cmos ? ppg00 8/16-bit ppg ch. 0 output pin cmp0_n comparator ch. 0 inverting analog input (negative input) pin 25 p90 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v4 lcd drive power supply pin 26 p91 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v3 lcd drive power supply pin 27 p92 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v2 lcd drive power supply pin 28 p93 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v1 lcd drive power supply pin 29 p94 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v0 lcd drive power supply pin 30 pb2 m general-purpose i/o port hysteresis cmos/ lcd ?? seg37 lcdc seg37 output pin 31 pb3 m general-purpose i/o port hysteresis cmos/ lcd ?? seg38 lcdc seg38 output pin 32 pb4 m general-purpose i/o port hysteresis cmos/ lcd ?? seg39 lcdc seg39 output pin 33 pa0 m general-purpose i/o port hysteresis cmos/ lcd ?? com0 lcdc com0 output pin 34 pa1 m general-purpose i/o port hysteresis cmos/ lcd ?? com1 lcdc com1 output pin 35 pa2 m general-purpose i/o port hysteresis cmos/ lcd ?? com2 lcdc com2 output pin 36 pa3 m general-purpose i/o port hysteresis cmos/ lcd ?? com3 lcdc com3 output pin 37 pa4 m general-purpose i/o port hysteresis cmos/ lcd ?? com4 lcdc com4 output pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 16 of 172 38 pa5 m general-purpose i/o port hysteresis cmos/ lcd ?? com5 lcdc com5 output pin 39 pa6 m general-purpose i/o port hysteresis cmos/ lcd ?? com6 lcdc com6 output pin 40 pa7 m general-purpose i/o port hysteresis cmos/ lcd ?? com7 lcdc com7 output pin 41 v ss ? power supply pin (gnd) ???? 42 pf1 b general-purpose i/o port hysteresis cmos ?? x1 main clock i/o oscillation pin 43 pf0 b general-purpose i/o port hysteresis cmos ?? x0 main clock input oscillation pin 44 c ? decoupling capacitor connection pin ???? 45 pg2 c general-purpose i/o port hysteresis cmos ? x1a subclock i/o oscillation pin 46 pg1 c general-purpose i/o port hysteresis cmos ? x0a subclock input oscillation pin 47 v cc ? power supply pin ???? 48 pf2 a general-purpose i/o port hysteresis cmos ? rst reset pin dedicated reset pin on mb95f714m/f716m/f718m 49 p17 h general-purpose i/o port hysteresis cmos ? cmp0_o comparator ch. 0 digital output pin 50 pb0 m general-purpose i/o port hysteresis cmos/ lcd ?? seg00 lcdc seg00 output pin 51 pb1 m general-purpose i/o port hysteresis cmos/ lcd ?? seg01 lcdc seg01 output pin 52 pc0 m general-purpose i/o port hysteresis cmos/ lcd ?? seg02 lcdc seg02 output pin 53 pc1 m general-purpose i/o port hysteresis cmos/ lcd ?? seg03 lcdc seg03 output pin 54 pc2 m general-purpose i/o port hysteresis cmos/ lcd ?? seg04 lcdc seg04 output pin 55 pc3 m general-purpose i/o port hysteresis cmos/ lcd ?? seg05 lcdc seg05 output pin 56 pc4 m general-purpose i/o port hysteresis cmos/ lcd ?? seg06 lcdc seg06 output pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 17 of 172 57 pc5 m general-purpose i/o port hysteresis cmos/ lcd ?? seg07 lcdc seg07 output pin 58 pc6 m general-purpose i/o port hysteresis cmos/ lcd ?? seg08 lcdc seg08 output pin 59 pc7 m general-purpose i/o port hysteresis cmos/ lcd ?? seg09 lcdc seg09 output pin 60 p60 m general-purpose i/o port hysteresis cmos/ lcd ?? seg10 lcdc seg10 output pin 61 p61 m general-purpose i/o port hysteresis cmos/ lcd ?? seg11 lcdc seg11 output pin 62 p62 m general-purpose i/o port hysteresis cmos/ lcd ?? seg12 lcdc seg12 output pin 63 p63 m general-purpose i/o port hysteresis cmos/ lcd ?? seg13 lcdc seg13 output pin 64 p64 m general-purpose i/o port hysteresis cmos/ lcd ?? seg14 lcdc seg14 output pin 65 p65 m general-purpose i/o port hysteresis cmos/ lcd ?? seg15 lcdc seg15 output pin 66 p66 m general-purpose i/o port hysteresis cmos/ lcd ?? seg16 lcdc seg16 output pin 67 p67 m general-purpose i/o port hysteresis cmos/ lcd ?? seg17 lcdc seg17 output pin 68 p43 m general-purpose i/o port hysteresis cmos/ lcd ?? seg18 lcdc seg18 output pin 69 p42 m general-purpose i/o port hysteresis cmos/ lcd ?? seg19 lcdc seg19 output pin 70 p41 m general-purpose i/o port hysteresis cmos/ lcd ?? seg20 lcdc seg20 output pin 71 p40 m general-purpose i/o port hysteresis cmos/ lcd ?? seg21 lcdc seg21 output pin 72 pe0 m general-purpose i/o port hysteresis cmos/ lcd ?? seg22 lcdc seg22 output pin 73 pe1 m general-purpose i/o port hysteresis cmos/ lcd ?? seg23 lcdc seg23 output pin 74 pe2 m general-purpose i/o port hysteresis cmos/ lcd ?? seg24 lcdc seg24 output pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 18 of 172 : available *1: for the i/o circuit types, see ?i/o circuit type?. *2: n-ch open drain *3: pull-up 75 pe3 m general-purpose i/o port hysteresis cmos/ lcd ?? seg25 lcdc seg25 output pin 76 pe4 m general-purpose i/o port hysteresis cmos/ lcd ?? seg26 lcdc seg26 output pin 77 pe5 m general-purpose i/o port hysteresis cmos/ lcd ?? seg27 lcdc seg27 output pin to11 8/16-bit composite timer ch. 1 output pin 78 pe6 m general-purpose i/o port hysteresis cmos/ lcd ?? seg28 lcdc seg28 output pin to10 8/16-bit composite timer ch. 1 output pin 79 pe7 m general-purpose i/o port hysteresis cmos/ lcd ?? seg29 lcdc seg27 output pin ec1 8/16-bit composite timer ch. 1 clock input pin 80 av ss ? power supply pin (gnd) for 8/12-bit a/d converter and comparator ???? pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 19 of 172 6. pin functions (mb95770m series) pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3 1av cc ? power supply pin for 8/12-bit a/d converter and comparator ???? 2 p07 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int07 external interrupt input pin an07 8/12-bit a/d conver ter analog input pin seg22 lcdc seg22 output pin 3 p06 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int06 external interrupt input pin an06 8/12-bit a/d conver ter analog input pin seg23 lcdc seg23 output pin 4 p05 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int05 external interrupt input pin an05 8/12-bit a/d conver ter analog input pin seg24 lcdc seg24 output pin uck1 uart/sio ch. 1 clock i/o pin 5 p04 v general-purpose i/o port cmos/ analog cmos/ lcd ?? int04 external interrupt input pin an04 8/12-bit a/d conver ter analog input pin seg25 lcdc seg25 output pin ui1 uart/sio ch. 1 data input pin 6 p03 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int03 external interrupt input pin an03 8/12-bit a/d conver ter analog input pin seg26 lcdc seg26 output pin uo1 uart/sio ch. 1 data output pin 7 p02 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int02 external interrupt input pin an02 8/12-bit a/d conver ter analog input pin seg27 lcdc seg27 output pin uck2 uart/sio ch. 2 clock i/o pin 8 p01 v general-purpose i/o port cmos/ analog cmos/ lcd ?? int01 external interrupt input pin an01 8/12-bit a/d conver ter analog input pin seg28 lcdc seg28 output pin to00 8/16-bit composite timer ch. 0 output pin ui2 uart/sio ch. 2 data input pin
mb95710m series mb95770m series document number: 002-09307 rev. *d page 20 of 172 9 p00 s general-purpose i/o port hysteresis/ analog cmos/ lcd ?? int00 external interrupt input pin an00 8/12-bit a/d conver ter analog input pin seg29 lcdc seg29 output pin uo2 uart/sio ch. 2 data output pin 10 p16 m general-purpose i/o port hysteresis cmos/ lcd ?? seg30 lcdc seg30 output pin ppg10 8/16-bit ppg ch. 1 output pin 11 p15 m general-purpose i/o port hysteresis cmos/ lcd ?? seg31 lcdc seg31 output pin ppg11 8/16-bit ppg ch. 1 output pin 12 p14 h general-purpose i/o port hysteresis cmos ? uck0 uart/sio ch. 0 clock i/o pin ec0 8/16-bit composite timer ch. 0 clock input pin ti0 16-bit reload timer ch. 0 input pin 13 p13 h general-purpose i/o port hysteresis cmos ? adtg 8/12-bit a/d converter trigger input pin to01 8/16-bit composite timer ch. 0 output pin 14 p12 d general-purpose i/o port hysteresis cmos ? dbg dbg input pin 15 p11 h general-purpose i/o port hysteresis cmos ? uo0 uart/sio ch. 0 data output pin 16 p10 g general-purpose i/o port cmos cmos ? ui0 uart/sio ch. 0 data input pin to0 16-bit reload timer ch. 0 output pin 17 p23 i general-purpose i/o port cmos cmos ? sda i 2 c bus interface ch. 0 data i/o pin 18 p22 i general-purpose i/o port cmos cmos ? scl i 2 c bus interface ch. 0 clock i/o pin 19 p21 t general-purpose i/o port hysteresis/ analog cmos ? ppg01 8/16-bit ppg ch. 0 output pin cmp0_p comparator ch. 0 non-inverting analog input (positive input) pin 20 p20 t general-purpose i/o port hysteresis/ analog cmos ? ppg00 8/16-bit ppg ch. 0 output pin cmp0_n comparator ch. 0 inverting analog input (negative input) pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 21 of 172 21 p90 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v4 lcd drive power supply pin 22 p91 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v3 lcd drive power supply pin 23 p92 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v2 lcd drive power supply pin 24 p93 r general-purpose i/o port hysteresis/ lcd power supply cmos/ lcd power supply ?? v1 lcd drive power supply pin 25 pa0 m general-purpose i/o port hysteresis cmos/ lcd ?? com0 lcdc com0 output pin 26 pa1 m general-purpose i/o port hysteresis cmos/ lcd ?? com1 lcdc com1 output pin 27 pa2 m general-purpose i/o port hysteresis cmos/ lcd ?? com2 lcdc com2 output pin 28 pa3 m general-purpose i/o port hysteresis cmos/ lcd ?? com3 lcdc com3 output pin 29 pa4 m general-purpose i/o port hysteresis cmos/ lcd ?? com4 lcdc com4 output pin 30 pa5 m general-purpose i/o port hysteresis cmos/ lcd ?? com5 lcdc com5 output pin 31 pa6 m general-purpose i/o port hysteresis cmos/ lcd ?? com6 lcdc com6 output pin 32 pa7 m general-purpose i/o port hysteresis cmos/ lcd ?? com7 lcdc com7 output pin 33 v ss ? power supply pin (gnd) ???? 34 pf1 b general-purpose i/o port hysteresis cmos ?? x1 main clock i/o oscillation pin 35 pf0 b general-purpose i/o port hysteresis cmos ?? x0 main clock input oscillation pin 36 c ? decoupling capacitor connection pin ???? 37 pg2 c general-purpose i/o port hysteresis cmos ? x1a subclock i/o oscillation pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 22 of 172 38 pg1 c general-purpose i/o port hysteresis cmos ? x0a subclock input oscillation pin 39 v cc ? power supply pin ???? 40 pf2 a general-purpose i/o port hysteresis cmos ? rst reset pin dedicated reset pin on mb95f774m/f776m/f778m 41 p17 h general-purpose i/o port hysteresis cmos ? cmp0_o comparator ch. 0 digital output pin 42 pb0 m general-purpose i/o port hysteresis cmos/ lcd ?? seg00 lcdc seg00 output pin 43 pb1 m general-purpose i/o port hysteresis cmos/ lcd ?? seg01 lcdc seg01 output pin 44 pc0 m general-purpose i/o port hysteresis cmos/ lcd ?? seg02 lcdc seg02 output pin 45 pc1 m general-purpose i/o port hysteresis cmos/ lcd ?? seg03 lcdc seg03 output pin 46 pc2 m general-purpose i/o port hysteresis cmos/ lcd ?? seg04 lcdc seg04 output pin 47 pc3 m general-purpose i/o port hysteresis cmos/ lcd ?? seg05 lcdc seg05 output pin 48 p60 m general-purpose i/o port hysteresis cmos/ lcd ?? seg06 lcdc seg06 output pin 49 p61 m general-purpose i/o port hysteresis cmos/ lcd ?? seg07 lcdc seg07 output pin 50 p62 m general-purpose i/o port hysteresis cmos/ lcd ?? seg08 lcdc seg08 output pin 51 p63 m general-purpose i/o port hysteresis cmos/ lcd ?? seg09 lcdc seg09 output pin 52 p64 m general-purpose i/o port hysteresis cmos/ lcd ?? seg10 lcdc seg10 output pin 53 p65 m general-purpose i/o port hysteresis cmos/ lcd ?? seg11 lcdc seg11 output pin 54 p66 m general-purpose i/o port hysteresis cmos/ lcd ?? seg12 lcdc seg12 output pin 55 p67 m general-purpose i/o port hysteresis cmos/ lcd ?? seg13 lcdc seg13 output pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 23 of 172 : available *1: for the i/o circuit types, see ?i/o circuit type?. *2: n-ch open drain *3: pull-up 56 pe0 m general-purpose i/o port hysteresis cmos/ lcd ?? seg14 lcdc seg14 output pin 57 pe1 m general-purpose i/o port hysteresis cmos/ lcd ?? seg15 lcdc seg15 output pin 58 pe2 m general-purpose i/o port hysteresis cmos/ lcd ?? seg16 lcdc seg16 output pin 59 pe3 m general-purpose i/o port hysteresis cmos/ lcd ?? seg17 lcdc seg17 output pin 60 pe4 m general-purpose i/o port hysteresis cmos/ lcd ?? seg18 lcdc seg18 output pin 61 pe5 m general-purpose i/o port hysteresis cmos/ lcd ?? seg19 lcdc seg19 output pin to11 8/16-bit composite timer ch. 1 output pin 62 pe6 m general-purpose i/o port hysteresis cmos/ lcd ?? seg20 lcdc seg20 output pin to10 8/16-bit composite timer ch. 1 output pin 63 pe7 m general-purpose i/o port hysteresis cmos/ lcd ?? seg21 lcdc seg21 output pin ec1 8/16-bit composite timer ch. 1 clock input pin 64 av ss ? power supply pin (gnd) for 8/12-bit a/d converter and comparator ???? pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 24 of 172 7. i/o circuit type type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx. 10 m ? cmos output ? hysteresis input ? pull-up control n-ch reset output / digital output reset input / hysteresis input standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control
mb95710m series mb95770m series document number: 002-09307 rev. *d page 25 of 172 type circuit remarks d ? n-ch open drain output ? hysteresis input g ? cmos output ?cmos input ? pull-up control h ? cmos output ? hysteresis input ? pull-up control i ? n-ch open drain output ?cmos input m ? cmos output ? lcd output ? hysteresis input r ? cmos output ? lcd power supply ? hysteresis input n-ch standby control hysteresis input digital output n-ch p-ch p-ch r pull-up control digital output digital output standby control cmos input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch standby control cmos input digital output n-ch p-ch digital output digital output lcd output lcd control standby control hysteresis input n-ch p-ch digital output digital output lcd control standby control hysteresis input lcd internal divider resistor i/o
mb95710m series mb95770m series document number: 002-09307 rev. *d page 26 of 172 type circuit remarks s ? cmos output ? lcd output ? hysteresis input ? analog input t ? cmos output ? hysteresis input ? analog input ? pull-up control v ? cmos output ?cmos input ? lcd output ? analog input n-ch p-ch digital output digital output analog input lcd output lcd control a/d control standby control hysteresis input n-ch p-ch r pull-up control digital output digital output analog input analog input control standby control hysteresis input n-ch p-ch digital output digital output analog input lcd output lcd control a/d control standby control cmos input
mb95710m series mb95770m series document number: 002-09307 rev. *d page 27 of 172 w ? cmos output ? hysteresis input ? analog input y ? cmos output ? hysteresis input type circuit remarks n-ch p-ch digital output digital output analog input analog input control standby control hysteresis input n-ch p-ch digital output digital output standby control hysteresis input
mb95710m series mb95770m series document number: 002-09307 rev. *d page 28 of 172 8. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failu re is greatly affected by the conditions in which they are used (circuit conditions, enviro nmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability fr om your cypress semiconductor devices. 8.1 precautions for product design this section describes precautions when designing electronic equipment usin g semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (v oltage, current, temperature, etc.) in excess of certain established limits, called abso lute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warran ted when operated within these ranges. always use semiconductor devices wit hin the recommended operating conditio ns. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating condit ions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative before- hand. ? processing and protection of pins these precautions must be followed when handling the pi ns which connect semiconductor devices to power supply and input/output functions. (1) preventing over-voltage and over-current conditions exposure to voltage or current levels in excess of maxi mum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over-current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present fo r extended periods of ti me can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch-up semiconductor devices are cons tructed by the formation of p-type and n-ty pe areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junc tions (called thyristor struct ures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch-up. caution: the occurrence of latch-up not only causes lo ss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 29 of 172 (2) be sure that abnormal current flows do not occur during the power-on sequence. ? observance of safety regulations and standards most countries in the world have established standards an d regulations regarding safety, protection from electromag- netic interference, etc. customers are requested to obse rve applicable regulations an d standards in the design of products. ? fail-safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by in corporating safety design measures into your facility and equipment su ch as redundancy, fire protection, and prevention of over-current le vels and other abnormal operating conditions. ? precautions related to usage of devices cypress semiconductor devices are intended for use in sta ndard applications (computers, office automation and other office equipment, industrial, communications, and measur ement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy co ntrols, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to co nsult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 8.2 precautions for package mounting package mounting may be either lead insertion type or surf ace mount type. in either case, for heat resistance during soldering, you should only mount under cypress?s recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed ci rcuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally in volves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applyi ng liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open conn ections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting tec hniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for ea ch product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. ? lead-free packaging caution: when ball grid ar ray (bga) packages with sn-ag-cu balls are mounted using sn-pb eutectic soldering, junction strength may be reduced under some conditions of use.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 30 of 172 ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natu ral environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and ca using packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5c and 30c. when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, cypress packages se miconductor devices in highly moisture -resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum lami nate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de-moistu rized by baking (heat drying). follow the cypress recom- mended conditions for baking. condition: 125c/24 h ? static electricity because semiconductor devic es are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humid ity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conduc tive floor mats and other me asures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti-static measures. (5) avoid the use of styrofoam or ot her highly static-prone materials for storage of completed board assemblies. 8.3 precautions for use environment reliability of semiconductor devices depends on ambien t temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in de vices as well as printed circuit boards. if high humidity levels are anticipated, consider anti-humidity processing. (2) discharge of static electricity when high-voltage charges exis t close to semiconductor devices, discha rges can cause abnormal operation. in such cases, use anti-static measures or processing to prevent discharges. (3) corrosive gase s, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions th at will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 31 of 172 (4) radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are fl ammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in ot her special environmental conditions should consult with sales repres entatives. 9. notes on device handling ? preventing latch-ups when using the device, ensure that the voltage app lied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pi n, or if a voltage out of the rating range of power sup- ply voltage mentioned in ?22.1 absolute maximum ratings? of ?electrical ch aracteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. ? stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluctuat es rapidly even though the fl uctuation is within the guar- anteed operating range of the v cc power supply voltage. as a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. ? notes on using the external clock when an external clock is used, oscilla tion stabilization wait time is required for power-on reset, wake-u p from sub- clock mode or stop mode. 10. pin connection ? treatment of unused pins if an unused input pin is left unconnected, a component ma y be permanently damaged due to malfunctions or latch- ups. always pull up or pull down an unused input pin through a resistor of at least 2 k . set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. if there is an unused outp ut pin, leave it unconnected. ? power supply pins to reduce unnecessary electro-magnetic emission, preven t malfunctions of strobe signals due to an increase in the ground level, and conform to the total out put current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addit ion, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a cera mic capacitor of approximately 1.0 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 32 of 172 ?dbg pin connect the dbg pin to an external pull-up resistor of 2 k or above. after power-on, ensure that the dbg pin does not st ay at ?l? level until the reset output is released. the dbg pin becomes a communication pin in debug mode. si nce the actual pull-up resi stance depends on the tool used and the interconnection length, refer to the t ool document when selecting a pull-up resistor. ?rst pin connect the rst pin to an external pull-up resistor of 2 k or above. to prevent the device from unintentionally entering the rese t mode due to noise, minimize the interconnection length between a pull-up resistor and the rst pin and that between a pull-up resistor and the v cc pin when designing the layout of the printed circuit board. the pf2/rst pin functions as the reset input/output pin after po wer-on. in addition, the reset output of the pf2/rst pin can be enabled by the rstoe bit in the sysc register, and the reset input function and the gen eral-purpo se i/o function can be selected by th e rsten bit in the sysc register. ? analog power supply always set the same potential to the av cc pin and the v cc pin. when v cc is larger than av cc , the current may flow through the an00 to an07 pins. ? treatment of power supply pins on the 8/12-bit a/d converter ensure that av cc is equal to v cc and av ss equal to v ss even when the 8/12-bit a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. therefore, connect a ceramic capacitor of 0.1 f (ap- prox.) as a bypass capacitor between the av cc pin and the av ss pin in the vicinity of this device. ?c pin use a ceramic capacitor or a capacitor with equivalent fr equency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, mini mize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. ? note on serial communication in serial communication, reception of wrong data may occur due to noise or other causes. therefore, design a printed circuit board to prevent noise from occurring. taking acco unt of the reception of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. if an error is de tected, retransmit the data. c cs dbg rst ? dbg/rst /c pins connection diagram
mb95710m series mb95770m series document number: 002-09307 rev. *d page 33 of 172 11. block diagram (mb95710m series) reset with lvd flash with security function (60/36/20 kbyte) f 2 mc-8fx cpu ram (2048/1024/512 bytes) interrupt controller oscillator circuit cr oscillator clock control on-chip debug wild register watch counter external interrupt uart/sio ch. 0 8/16-bit composite timer ch. 0 8/12-bit a/d converter 16-bit reload timer ch. 0 8/16-bit composite timer ch. 1 uart/sio ch. 1 i 2 c bus interface ch. 0 8/16-bit ppg ch. 0 8/16-bit ppg ch. 1 port port pf2 *1 /rst *2 pf0/x0 *2 pf1/x1 *2 pg1/x0a *2 pg2/x1a *2 p00/int00 to p07/int07 c p14/uck0 p11/uo0 p10/ui0 p05/uck1 p03/uo1 p04/ui1 uart/sio ch. 2 p02/uck2 p00/uo2 p01/ui2 p20/ppg00 p21/ppg01 p15/ppg11 p16/ppg10 p22 *1 /scl p23 *1 /sda p12 *1 /dbg p52/to00 p50/to01 p51/ec0 p00/an00 to p07/an07 p13/adtg lcdc (4 com or 8 com) p90/v4 to p94/v0 pa0/com0 to pa3/com3 pb0/seg00, pb1/seg01 pc0/seg02 to pc7/seg09 p60/seg10 to p67/seg17 p43/seg18 to p40/seg21 pe0/seg22 to pe7/seg29 p07/seg30 to p01/seg36 pb2/seg37 to pb4/seg39 p90/v4 to p94/v0 4 com mode: 8 com mode: pa0/com0 to pa7/com7 pb0/seg00, pb1/seg01 pc0/seg02 to pc7/seg09 p60/seg10 to p67/seg17 p43/seg18 to p40/seg21 pe0/seg22 to pe7/seg29 p07/seg30 to p02/seg35 pe5/to11 pe6/to10 pe7/ec1 comparator ch. 0 p20/cmp0_n p21/cmp0_p p17/cmp0_o p52/ti0 p53/to0 vcc vss *1: *2: *3: p12, p22, p23 and pf2 are n-ch open drain pins. software option when the event counter operation mode is enabled, 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as a n event counter. internal bus *3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 34 of 172 12. block diagram (mb95770m series) reset with lvd flash with security function (60/36/20 kbyte) f 2 mc-8fx cpu ram (2048/1024/512 bytes) interrupt controller oscillator circuit cr oscillator clock control on-chip debug wild register watch counter external interrupt uart/sio ch. 0 8/16-bit composite timer ch. 0 8/12-bit a/d converter 16-bit reload timer ch. 0 8/16-bit composite timer ch. 1 uart/sio ch. 1 i 2 c bus interface ch. 0 8/16-bit ppg ch. 0 8/16-bit ppg ch. 1 port port pf2 *1 /rst *2 pf0/x0 *2 pf1/x1 *2 pg1/x0a *2 pg2/x1a *2 p00/int00 to p07/int07 c p14/uck0 p11/uo0 p10/ui0 p05/uck1 p03/uo1 p04/ui1 uart/sio ch. 2 p02/uck2 p00/uo2 p01/ui2 p20/ppg00 p21/ppg01 p16/ppg10 p15/ppg11 p22 *1 /scl p23 *1 /sda p12 *1 /dbg p01/to00 p13/to01 p14/ec0 p00/an00 to p07/an07 p13/adtg lcdc (4 com or 8 com) p90/v4 to p93/v1 pa0/com0 to pa3/com3 pb0/seg00, pb1/seg01 pc0/seg02 to pc3/seg05 p60/seg06 to p67/seg13 pe0/seg14 to pe7/seg21 p07/seg22 to p00/seg29 p16/seg30, p15/seg31 p90/v4 to p93/v1 4 com mode: 8 com mode: pa0/com0 to pa7/com7 pb0/seg00, pb1/seg01 pc0/seg02 to pc3/seg05 p60/seg06 to p67/seg13 pe0/seg14 to pe7/seg21 p07/seg22 to p02/seg27 pe5/to11 pe6/to10 pe7/ec1 comparator ch. 0 p20/cmp0_n p21/cmp0_p p17/cmp0_o p14/ti0 p10/to0 vcc vss *1: *2: *3: p12, p22, p23 and pf2 are n-ch open drain pins. software option when the event counter operation mode is enabled, 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as a n event counter. internal bus *3
mb95710m series mb95770m series document number: 002-09307 rev. *d page 35 of 172 13. cpu core ? memory space the memory space of the mb95710m/770m series is 64 kbyt e in size, and consists of an i/o area, an extended i/o area, a data area, and a program area. the memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. the memo ry maps of the mb95710m/770m series are shown below. ? memory maps mb95f714j/f714m mb95f774j/f774m i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 flash memory 4 kbyte 0x1000 0x2000 flash memory 4 kbyte extended i/o area 0x0f80 0x1000 access prohibited access prohibited 0x8000 0x2000 access prohibited 0xc000 ram 512 bytes flash memory 16 kbyte 0x0290 0xffff mb95f716j/f716m mb95f776j/f776m i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 extended i/o area 0x0f80 access prohibited ram 1 kbyte flash memory 32 kbyte 0x0490 0xffff 0x1000 mb95f718j/f718m mb95f778j/f778m i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 extended i/o area 0x0f80 access prohibited ram 2 kbyte flash memory 60 kbyte 0x0890 0xffff
mb95710m series mb95770m series document number: 002-09307 rev. *d page 36 of 172 14. memory space the memory space of the mb95710m/770m series is 64 kbyt e in size, and consists of an i/o area, an extended i/o area, a data area, and a program area. the memory space in cludes areas for specific applications such as general- purpose registers and a vector table. ? i/o area (addresses: 0x0000 to 0x007f) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the i/o area forms part of the memory space, it can be accessed in the same way as the memory. it can also be accessed at high-speed by using direct addressing instructions. ? extended i/o area (addresses: 0x0f80 to 0x0fff) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the extended i/o area forms part of the memory space, it can be accessed in the same way as the memory. ? data area ? static ram is incorporated in the data area as the internal data area. ? the internal ram size varies according to product. ? the ram area from 0x0090 to 0x00ff can be accessed at high-speed by using dire ct addressing instructions. ? in mb95f716j/f716m/f718j/f718m/f776j/f776m/f778j/f778m, the area from 0x0090 to 0x047f is an extend- ed direct addressing area. it can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. ? in mb95f714j/f714m/f774j/f774m, the area from 0x0090 to 0x028f is an extended direct addressing area. it can be accessed at high-speed by direct addressi ng instructions with a direct bank pointer set. ? the area from 0x0100 to 0x01ff can be used as a general-purpose register area. ? program area ? the flash memory is incorporated in the program area as the internal program area. ? the flash memory size varies according to product. ? the area from 0xffc0 to 0xffff is used as the vector table. ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 37 of 172 ? memory space map direct addressing area extended direct addressing area i/o area access prohibited 0x0000 0x0080 0x0090 registers (general-purpose register area) 0x0100 0x0200 0x047f vector table area extended i/o area 0x0f80 0x0fff 0x1000 access prohibited program area data area 0x088f 0x0890 0xffff 0xffc0
mb95710m series mb95770m series document number: 002-09307 rev. *d page 38 of 172 15. areas for spec ific applications the general-purpose register area and vector tabl e area are used for the specific applications. ? general-purpose register area (addresses: 0x0100 to 0x01ff) ? this area contains the auxiliary registers used fo r 8-bit arithmetic opera tions, transfer, etc. ? as this area forms part of the ram area, it can also be used as conventional ram. ? when the area is used as general-pur pose registers, general-purpose regist er addressing enables high-speed ac- cess with short instructions. ? non-volatile register data area (addresses: 0xffbb to 0xffbf) ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register. for details, refer to ?chapter 28 non-volatile register (nvr) interface? in ?new 8fx mb95710m/770m series hardware manual? ? vector table area (addresses: 0xffc0 to 0xffff) ? this area is used as the vector table for vector call instructions (callv), interrupts, and resets. ? the top of the flash memory area is allocated to the vect or table area. the start address of a service routine is set to an address in the vector table in the form of data. ?interrupt source table? lists the vect or table addresses corresponding to vector call instructions, interrupts, and re- sets. for details, refer to ?chapter 4 reset?, ?chapter 5 interrupts?, and ?a.2 special instruction special in- struction callv #vct? in ?appendix? in ?new 8fx mb95710m/770m series hardware manual?. ? direct bank pointer and access area *: due to the memory size limit, the available access area is up to ?0x028f? in mb95f714j/f714m/f774j/ f774m. direct bank pointer (dp[2:0]) operand-specified dir access area 0bxxx (it does not affect mapping. ) 0x0000 to 0x007f 0x0000 to 0x007f 0b000 (initial value) 0x0090 to 0x00ff 0x0090 to 0x00ff 0b001 0x0080 to 0x00ff 0x0100 to 0x017f 0b010 0x0180 to 0x01ff 0b011 0x0200 to 0x027f 0b100 0x0280 to 0x02ff* 0b101 0x0300 to 0x037f 0b110 0x0380 to 0x03ff 0b111 0x0400 to 0x047f
mb95710m series mb95770m series document number: 002-09307 rev. *d page 39 of 172 16. i/o map (m b95710m series) address register abbreviation register name r/w initial value 0x0000 pdr0 port 0 data register r/w 0b00000000 0x0001 ddr0 port 0 directio n register r/w 0b00000000 0x0002 pdr1 port 1 data register r/w 0b00000000 0x0003 ddr1 port 1 directio n register r/w 0b00000000 0x0004 ? (disabled) ? ? 0x0005 watr oscillation stabilization wait time setting register r/w 0b11111111 0x0006 pllc pll control register r/w 0b000x0000 0x0007 sycc system clock cont rol register r/w 0bxxx11011 0x0008 stbc standby control register r/w 0b00000000 0x0009 rsrr reset source register r/w 0b000xxxxx 0x000a tbtc time-base timer control register r/w 0b00000000 0x000b wpcr watch prescaler control register r/w 0b00000000 0x000c wdtc watchdog timer control register r/w 0b00xx0000 0x000d sycc2 system clock control register 2 r/w 0bxxxx0011 0x000e pdr2 port 2 data register r/w 0b00000000 0x000f ddr2 port 2 direction register r/w 0b00000000 0x0010, 0x0011 ? (disabled) ? ? 0x0012 pdr4 port 4 data register r/w 0b00000000 0x0013 ddr4 port 4 directio n register r/w 0b00000000 0x0014 pdr5 port 5 data register r/w 0b00000000 0x0015 ddr5 port 5 directio n register r/w 0b00000000 0x0016 pdr6 port 6 data register r/w 0b00000000 0x0017 ddr6 port 6 directio n register r/w 0b00000000 0x0018 to 0x001b ? (disabled) ? ? 0x001c pdr9 port 9 data register r/w 0b00000000 0x001d ddr9 port 9 directio n register r/w 0b00000000 0x001e pdra port a data register r/w 0b00000000 0x001f ddra port a direction register r/w 0b00000000 0x0020 pdrb port b data register r/w 0b00000000 0x0021 ddrb port b direction register r/w 0b00000000 0x0022 pdrc port c data register r/w 0b00000000 0x0023 ddrc port c direction register r/w 0b00000000 0x0024, 0x0025 ? (disabled) ? ?
mb95710m series mb95770m series document number: 002-09307 rev. *d page 40 of 172 0x0026 pdre port e data register r/w 0b00000000 0x0027 ddre port e direction register r/w 0b00000000 0x0028 pdrf port f data register r/w 0b00000000 0x0029 ddrf port f direction register r/w 0b00000000 0x002a pdrg port g data register r/w 0b00000000 0x002b ddrg port g direction register r/w 0b00000000 0x002c ? (disabled) ? ? 0x002d pul1 port 1 pull-up register r/w 0b00000000 0x002e pul2 port 2 pull-up register r/w 0b00000000 0x002f, 0x0030 ? (disabled) ? ? 0x0031 pul5 port 5 pull-up register r/w 0b00000000 0x0032 to 0x0034 ? (disabled) ? ? 0x0035 pulg port g pull-up register r/w 0b00000000 0x0036 t01cr1 8/16-bit composite timer 01 status control register 1 r/w 0b00000000 0x0037 t00cr1 8/16-bit composite timer 00 status control register 1 r/w 0b00000000 0x0038 t11cr1 8/16-bit composite timer 11 status control register 1 r/w 0b00000000 0x0039 t10cr1 8/16-bit composite timer 10 status control register 1 r/w 0b00000000 0x003a pc01 8/16-bit ppg timer 01 control register r/w 0b00000000 0x003b pc00 8/16-bit ppg timer 00 control register r/w 0b00000000 0x003c pc11 8/16-bit ppg timer 11 control register r/w 0b00000000 0x003d pc10 8/16-bit ppg timer 10 control register r/w 0b00000000 0x003e tmcsrh0 16-bit reload timer control st atus register (upper) ch. 0 r/w 0b00000000 0x003f tmcsrl0 16-bit reload timer control st atus register (lower) ch. 0 r/w 0b00000000 0x0040 to 0x0047 ? (disabled) ? ? 0x0048 eic00 external interrupt circuit control register ch. 0/ch. 1 r/w 0b00000000 0x0049 eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 0b00000000 0x004a eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 0b00000000 0x004b eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 0b00000000 0x004c, 0x004d ? (disabled) ? ? 0x004e lvdc lvd control register r/w 0b00000100 0x004f lcdcc2 lcdc control register 2 r/w 0b00010100 0x0050 cmr0 comparator control register ch. 0 r/w 0b00000001 address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 41 of 172 0x0051 to 0x0055 ? (disabled) ? ? 0x0056 smc10 uart/sio serial mode control register 1 ch. 0 r/w 0b00000000 0x0057 smc20 uart/sio serial mode control register 2 ch. 0 r/w 0b00100000 0x0058 ssr0 uart/sio serial status and data register ch. 0 r/w 0b00000001 0x0059 tdr0 uart/sio serial output data register ch. 0 r/w 0b00000000 0x005a rdr0 uart/sio serial input data register ch. 0 r 0b00000000 0x005b smc11 uart/sio serial mode control register 1 ch. 1 r/w 0b00000000 0x005c smc21 uart/sio serial mode control register 2 ch. 1 r/w 0b00100000 0x005d ssr1 uart/sio serial status and data register ch. 1 r/w 0b00000001 0x005e tdr1 uart/sio serial output data register ch. 1 r/w 0b00000000 0x005f rdr1 uart/sio serial input data register ch. 1 r 0b00000000 0x0060 ibcr00 i 2 c bus control register 0 ch. 0 r/w 0b00000000 0x0061 ibcr10 i 2 c bus control register 1 ch. 0 r/w 0b00000000 0x0062 ibsr0 i 2 c bus status register ch. 0 r/w 0b00000000 0x0063 iddr0 i 2 c data register ch. 0 r/w 0b00000000 0x0064 iaar0 i 2 c address register ch. 0 r/w 0b00000000 0x0065 iccr0 i 2 c clock control register ch. 0 r/w 0b00000000 0x0066 smc12 uart/sio serial mode control register 1 ch. 2 r/w 0b00000000 0x0067 smc22 uart/sio serial mode control register 2 ch. 2 r/w 0b00100000 0x0068 ssr2 uart/sio serial status and data register ch. 2 r/w 0b00000001 0x0069 tdr2 uart/sio serial output data register ch. 2 r/w 0b00000000 0x006a rdr2 uart/sio serial input data register ch. 2 r 0b00000000 0x006b adc3 8/12-bit a/d converte r control register 3 r/w 0b01111100 0x006c adc1 8/12-bit a/d converter control register 1 r/w 0b00000000 0x006d adc2 8/12-bit a/d converter control register 2 r/w 0b00000000 0x006e addh 8/12-bit a/d converter data register (upper) r/w 0b00000000 0x006f addl 8/12-bit a/d converter data register (lower) r/w 0b00000000 0x0070 wcsr watch counter control register r/w 0b00000000 0x0071 fsr2 flash memory stat us register 2 r/w 0b00000000 0x0072 fsr flash memory status register r/w 0b000x0000 0x0073 swre0 flash memory sector wr ite control register 0 r/w 0b00000000 0x0074 fsr3 flash memory st atus register 3 r 0b000xxxxx 0x0075 fsr4 flash memory stat us register 4 r/w 0b00000000 0x0076 wren wild register address compare enable register r/w 0b00000000 0x0077 wror wild register data test setting register r/w 0b00000000 address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 42 of 172 0x0078 ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0x0079 ilr0 interrupt level setting register 0 r/w 0b11111111 0x007a ilr1 interrupt level setting register 1 r/w 0b11111111 0x007b ilr2 interrupt level setting register 2 r/w 0b11111111 0x007c ilr3 interrupt level setting register 3 r/w 0b11111111 0x007d ilr4 interrupt level setting register 4 r/w 0b11111111 0x007e ilr5 interrupt level setting register 5 r/w 0b11111111 0x007f ? (disabled) ? ? 0x0f80 wrarh0 wild register address sett ing register (upper) ch. 0 r/w 0b00000000 0x0f81 wrarl0 wild register address setting register (lower) ch. 0 r/w 0b00000000 0x0f82 wrdr0 wild register data setting register ch. 0 r/w 0b00000000 0x0f83 wrarh1 wild register address sett ing register (upper) ch. 1 r/w 0b00000000 0x0f84 wrarl1 wild register address setting register (lower) ch. 1 r/w 0b00000000 0x0f85 wrdr1 wild register data setting register ch. 1 r/w 0b00000000 0x0f86 wrarh2 wild register address sett ing register (upper) ch. 2 r/w 0b00000000 0x0f87 wrarl2 wild register address setting register (lower) ch. 2 r/w 0b00000000 0x0f88 wrdr2 wild register data setting register ch. 2 r/w 0b00000000 0x0f89 to 0x0f91 ? (disabled) ? ? 0x0f92 t01cr0 8/16-bit composite timer 01 status control register 0 r/w 0b00000000 0x0f93 t00cr0 8/16-bit composite timer 00 status control register 0 r/w 0b00000000 0x0f94 t01dr 8/16-bit composite timer 01 data register r/w 0b00000000 0x0f95 t00dr 8/16-bit composite timer 00 data register r/w 0b00000000 0x0f96 tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 0b00000000 0x0f97 t11cr0 8/16-bit composite timer 11 status control register 0 r/w 0b00000000 0x0f98 t10cr0 8/16-bit composite timer 10 status control register 0 r/w 0b00000000 0x0f99 t11dr 8/16-bit composite timer 11 data register r/w 0b00000000 0x0f9a t10dr 8/16-bit composite time r 10 data register r/w 0b00000000 0x0f9b tmcr1 8/16-bit composite timer 10/11 timer mode control register r/w 0b00000000 0x0f9c pps01 8/16-bit ppg01 cycle se tting buffer register r/w 0b11111111 0x0f9d pps00 8/16-bit ppg00 cycle se tting buffer register r/w 0b11111111 0x0f9e pds01 8/16-bit ppg01 duty setting buffer register r/w 0b11111111 0x0f9f pds00 8/16-bit ppg00 duty setting buffer register r/w 0b11111111 0x0fa0 pps11 8/16-bit ppg11 cycle sett ing buffer register r/w 0b11111111 address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 43 of 172 0x0fa1 pps10 8/16-bit ppg10 cycle se tting buffer register r/w 0b11111111 0x0fa2 pds11 8/16-bit ppg11 duty setting buffer register r/w 0b11111111 0x0fa3 pds10 8/16-bit ppg10 duty setting buffer register r/w 0b11111111 0x0fa4 ppgs 8/16-bit ppg start register r/w 0b00000000 0x0fa5 revc 8/16-bit ppg output inversion register r/w 0b00000000 0x0fa6 tmrh0 16-bit reload timer timer register (upper) ch. 0 r/w 0b00000000 tmrlrh0 16-bit reload timer reload register (upper) ch. 0 0x0fa7 tmrl0 16-bit reload timer timer register (lower) ch. 0 r/w 0b00000000 tmrlrl0 16-bit reload timer reload register (lower) ch. 0 0x0fa8 pssr0 uart/sio dedicated baud rate generator prescaler select register ch. 0 r/w 0b00000000 0x0fa9 brsr0 uart/sio dedicated baud rate generator baud rate setting register ch. 0 r/w 0b00000000 0x0faa pssr1 uart/sio dedicated baud rate generator prescaler select register ch. 1 r/w 0b00000000 0x0fab brsr1 uart/sio dedicated baud rate generator baud rate setting register ch. 1 r/w 0b00000000 0x0fac pssr2 uart/sio dedicated baud rate generator prescaler select register ch. 2 r/w 0b00000000 0x0fad brsr2 uart/sio dedicated baud rate generator baud rate setting register ch. 2 r/w 0b00000000 0x0fae ? (disabled) ? ? 0x0faf aidrl a/d input disable register (lower) r/w 0b00000000 0x0fb0 lcdcc1 lcdc control register 1 r/w 0b00000000 0x0fb1 ? (disabled) ? ? 0x0fb2 lcdce1 lcdc enable register 1 r/w 0b00111110 0x0fb3 lcdce2 lcdc enable register 2 r/w 0b00000000 0x0fb4 lcdce3 lcdc enable register 3 r/w 0b00000000 0x0fb5 lcdce4 lcdc enable register 4 r/w 0b00000000 0x0fb6 lcdce5 lcdc enable register 5 r/w 0b00000000 0x0fb7 lcdce6 lcdc enable register 6 r/w 0b00000000 0x0fb8 lcdce7 lcdc enable register 7 r/w 0b00000000 0x0fb9 lcdcb1 lcdc blinking setting register 1 r/w 0b00000000 0x0fba lcdcb2 lcdc blinking setting register 2 r/w 0b00000000 0x0fbb, 0x0fbc ? (disabled) ? ? 0x0fbd to 0x0fe0 lcdram lcdc display ram (36 bytes) r/w 0b00000000 address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 44 of 172 ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. 0x0fe1 ? (disabled) ? ? 0x0fe2 evcr event counter control register r/w 0b00000000 0x0fe3 wcdr watch counter data register r/w 0b00111111 0x0fe4 crth main cr clock trimmi ng register (u pper) r/w 0b000xxxxx 0x0fe5 crtl main cr clock trimmi ng register (lower) r/w 0b000xxxxx 0x0fe6 sysc2 system configuratio n register 2 r/w 0b00000000 0x0fe7 crtda main cr clock temperature dependent adjustment register r/w 0b000xxxxx 0x0fe8 sysc system configurat ion register r/w 0b00111111 0x0fe9 cmcr clock monitoring control register r/w 0b00000000 0x0fea cmdr clock monitoring data register r 0b00000000 0x0feb wdth watchdog timer selecti on id register (upper) r 0bxxxxxxxx 0x0fec wdtl watchdog timer selecti on id register (lower) r 0bxxxxxxxx 0x0fed, 0x0fee ? (disabled) ? ? 0x0fef wicr interrupt pin selection circuit control register r/w 0b01000000 0x0ff0 to 0x0fff ? (disabled) ? ? r/w : readable/writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 45 of 172 17. i/o map (m b95770m series) address register abbreviation register name r/w initial value 0x0000 pdr0 port 0 data register r/w 0b00000000 0x0001 ddr0 port 0 directio n register r/w 0b00000000 0x0002 pdr1 port 1 data register r/w 0b00000000 0x0003 ddr1 port 1 directio n register r/w 0b00000000 0x0004 ? (disabled) ? ? 0x0005 watr oscillation stabilization wait time setting register r/w 0b11111111 0x0006 pllc pll control register r/w 0b000x0000 0x0007 sycc system clock cont rol register r/w 0bxxx11011 0x0008 stbc standby control register r/w 0b00000000 0x0009 rsrr reset source register r/w 0b000xxxxx 0x000a tbtc time-base timer control register r/w 0b00000000 0x000b wpcr watch prescaler control register r/w 0b00000000 0x000c wdtc watchdog timer control register r/w 0b00xx0000 0x000d sycc2 system clock control register 2 r/w 0bxxxx0011 0x000e pdr2 port 2 data register r/w 0b00000000 0x000f ddr2 port 2 direction register r/w 0b00000000 0x0010 to 0x0015 ? (disabled) ? ? 0x0016 pdr6 port 6 data register r/w 0b00000000 0x0017 ddr6 port 6 directio n register r/w 0b00000000 0x0018 to 0x001b ? (disabled) ? ? 0x001c pdr9 port 9 data register r/w 0b00000000 0x001d ddr9 port 9 directio n register r/w 0b00000000 0x001e pdra port a data register r/w 0b00000000 0x001f ddra port a direction register r/w 0b00000000 0x0020 pdrb port b data register r/w 0b00000000 0x0021 ddrb port b direction register r/w 0b00000000 0x0022 pdrc port c data register r/w 0b00000000 0x0023 ddrc port c direction register r/w 0b00000000 0x0024, 0x0025 ? (disabled) ? ? 0x0026 pdre port e data register r/w 0b00000000 0x0027 ddre port e direction register r/w 0b00000000 0x0028 pdrf port f data register r/w 0b00000000
mb95710m series mb95770m series document number: 002-09307 rev. *d page 46 of 172 0x0029 ddrf port f direction register r/w 0b00000000 0x002a pdrg port g data register r/w 0b00000000 0x002b ddrg port g direction register r/w 0b00000000 0x002c ? (disabled) ? ? 0x002d pul1 port 1 pull-up register r/w 0b00000000 0x002e pul2 port 2 pull-up register r/w 0b00000000 0x002f to 0x0034 ? (disabled) ? ? 0x0035 pulg port g pull-up register r/w 0b00000000 0x0036 t01cr1 8/16-bit composite timer 01 status control register 1 r/w 0b00000000 0x0037 t00cr1 8/16-bit composite timer 00 status control register 1 r/w 0b00000000 0x0038 t11cr1 8/16-bit composite timer 11 status control register 1 r/w 0b00000000 0x0039 t10cr1 8/16-bit composite timer 10 status control register 1 r/w 0b00000000 0x003a pc01 8/16-bit ppg timer 01 control register r/w 0b00000000 0x003b pc00 8/16-bit ppg timer 00 control register r/w 0b00000000 0x003c pc11 8/16-bit ppg timer 11 control register r/w 0b00000000 0x003d pc10 8/16-bit ppg timer 10 control register r/w 0b00000000 0x003e tmcsrh0 16-bit reload timer control st atus register (upper) ch. 0 r/w 0b00000000 0x003f tmcsrl0 16-bit reload timer control st atus register (lower) ch. 0 r/w 0b00000000 0x0040 to 0x0047 ? (disabled) ? ? 0x0048 eic00 external interrupt circuit control register ch. 0/ch. 1 r/w 0b00000000 0x0049 eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 0b00000000 0x004a eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 0b00000000 0x004b eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 0b00000000 0x004c, 0x004d ? (disabled) ? ? 0x004e lvdc lvd control register r/w 0b00000100 0x004f lcdcc2 lcdc control register 2 r/w 0b00010100 0x0050 cmr0 comparator control register ch. 0 r/w 0b00000001 0x0051 to 0x0055 ? (disabled) ? ? 0x0056 smc10 uart/sio serial mode control register 1 ch. 0 r/w 0b00000000 0x0057 smc20 uart/sio serial mode control register 2 ch. 0 r/w 0b00100000 0x0058 ssr0 uart/sio serial status and data register ch. 0 r/w 0b00000001 0x0059 tdr0 uart/sio serial output data register ch. 0 r/w 0b00000000 address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 47 of 172 0x005a rdr0 uart/sio serial input data register ch. 0 r 0b00000000 0x005b smc11 uart/sio serial mode control register 1 ch. 1 r/w 0b00000000 0x005c smc21 uart/sio serial mode control register 2 ch. 1 r/w 0b00100000 0x005d ssr1 uart/sio serial status and data register ch. 1 r/w 0b00000001 0x005e tdr1 uart/sio serial output data register ch. 1 r/w 0b00000000 0x005f rdr1 uart/sio serial input data register ch. 1 r 0b00000000 0x0060 ibcr00 i 2 c bus control register 0 ch. 0 r/w 0b00000000 0x0061 ibcr10 i 2 c bus control register 1 ch. 0 r/w 0b00000000 0x0062 ibsr0 i 2 c bus status register ch. 0 r/w 0b00000000 0x0063 iddr0 i 2 c data register ch. 0 r/w 0b00000000 0x0064 iaar0 i 2 c address register ch. 0 r/w 0b00000000 0x0065 iccr0 i 2 c clock control register ch. 0 r/w 0b00000000 0x0066 smc12 uart/sio serial mode control register 1 ch. 2 r/w 0b00000000 0x0067 smc22 uart/sio serial mode control register 2 ch. 2 r/w 0b00100000 0x0068 ssr2 uart/sio serial status and data register ch. 2 r/w 0b00000001 0x0069 tdr2 uart/sio serial output data register ch. 2 r/w 0b00000000 0x006a rdr2 uart/sio serial input data register ch. 2 r 0b00000000 0x006b adc3 8/12-bit a/d converte r control register 3 r/w 0b01111100 0x006c adc1 8/12-bit a/d converter control register 1 r/w 0b00000000 0x006d adc2 8/12-bit a/d converter control register 2 r/w 0b00000000 0x006e addh 8/12-bit a/d converter data register (upper) r/w 0b00000000 0x006f addl 8/12-bit a/d converter data register (lower) r/w 0b00000000 0x0070 wcsr watch counter control register r/w 0b00000000 0x0071 fsr2 flash memory stat us register 2 r/w 0b00000000 0x0072 fsr flash memory status register r/w 0b000x0000 0x0073 swre0 flash memory sector wr ite control register 0 r/w 0b00000000 0x0074 fsr3 flash memory st atus register 3 r 0b000xxxxx 0x0075 fsr4 flash memory stat us register 4 r/w 0b00000000 0x0076 wren wild register address compare enable register r/w 0b00000000 0x0077 wror wild register data test setting register r/w 0b00000000 0x0078 ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0x0079 ilr0 interrupt level setting register 0 r/w 0b11111111 0x007a ilr1 interrupt level setting register 1 r/w 0b11111111 0x007b ilr2 interrupt level setting register 2 r/w 0b11111111 0x007c ilr3 interrupt level setting register 3 r/w 0b11111111 0x007d ilr4 interrupt level setting register 4 r/w 0b11111111 address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 48 of 172 0x007e ilr5 interrupt level setting register 5 r/w 0b11111111 0x007f ? (disabled) ? ? 0x0f80 wrarh0 wild register address sett ing register (upper) ch. 0 r/w 0b00000000 0x0f81 wrarl0 wild register address setting register (lower) ch. 0 r/w 0b00000000 0x0f82 wrdr0 wild register data setting register ch. 0 r/w 0b00000000 0x0f83 wrarh1 wild register address sett ing register (upper) ch. 1 r/w 0b00000000 0x0f84 wrarl1 wild register address setting register (lower) ch. 1 r/w 0b00000000 0x0f85 wrdr1 wild register data setting register ch. 1 r/w 0b00000000 0x0f86 wrarh2 wild register address sett ing register (upper) ch. 2 r/w 0b00000000 0x0f87 wrarl2 wild register address setting register (lower) ch. 2 r/w 0b00000000 0x0f88 wrdr2 wild register data setting register ch. 2 r/w 0b00000000 0x0f89 to 0x0f91 ? (disabled) ? ? 0x0f92 t01cr0 8/16-bit composite timer 01 status control register 0 r/w 0b00000000 0x0f93 t00cr0 8/16-bit composite timer 00 status control register 0 r/w 0b00000000 0x0f94 t01dr 8/16-bit composite timer 01 data register r/w 0b00000000 0x0f95 t00dr 8/16-bit composite timer 00 data register r/w 0b00000000 0x0f96 tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 0b00000000 0x0f97 t11cr0 8/16-bit composite timer 11 status control register 0 r/w 0b00000000 0x0f98 t10cr0 8/16-bit composite timer 10 status control register 0 r/w 0b00000000 0x0f99 t11dr 8/16-bit composite timer 11 data register r/w 0b00000000 0x0f9a t10dr 8/16-bit composite time r 10 data register r/w 0b00000000 0x0f9b tmcr1 8/16-bit composite timer 10/11 timer mode control register r/w 0b00000000 0x0f9c pps01 8/16-bit ppg01 cycle se tting buffer register r/w 0b11111111 0x0f9d pps00 8/16-bit ppg00 cycle se tting buffer register r/w 0b11111111 0x0f9e pds01 8/16-bit ppg01 duty setting buffer register r/w 0b11111111 0x0f9f pds00 8/16-bit ppg00 duty setting buffer register r/w 0b11111111 0x0fa0 pps11 8/16-bit ppg11 cycle sett ing buffer register r/w 0b11111111 0x0fa1 pps10 8/16-bit ppg10 cycle se tting buffer register r/w 0b11111111 0x0fa2 pds11 8/16-bit ppg11 duty setting buffer register r/w 0b11111111 0x0fa3 pds10 8/16-bit ppg10 duty setting buffer register r/w 0b11111111 0x0fa4 ppgs 8/16-bit ppg start register r/w 0b00000000 0x0fa5 revc 8/16-bit ppg output inversion register r/w 0b00000000 0x0fa6 tmrh0 16-bit reload timer timer register (upper) ch. 0 r/w 0b00000000 tmrlrh0 16-bit reload timer reload register (upper) ch. 0 address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 49 of 172 0x0fa7 tmrl0 16-bit reload timer timer register (lower) ch. 0 r/w 0b00000000 tmrlrl0 16-bit reload timer reload register (lower) ch. 0 0x0fa8 pssr0 uart/sio dedicated baud rate generator prescaler select register ch. 0 r/w 0b00000000 0x0fa9 brsr0 uart/sio dedicated baud rate generator baud rate setting register ch. 0 r/w 0b00000000 0x0faa pssr1 uart/sio dedicated baud rate generator prescaler select register ch. 1 r/w 0b00000000 0x0fab brsr1 uart/sio dedicated baud rate generator baud rate setting register ch. 1 r/w 0b00000000 0x0fac pssr2 uart/sio dedicated baud rate generator prescaler select register ch. 2 r/w 0b00000000 0x0fad brsr2 uart/sio dedicated baud rate generator baud rate setting register ch. 2 r/w 0b00000000 0x0fae ? (disabled) ? ? 0x0faf aidrl a/d input disable register (lower) r/w 0b00000000 0x0fb0 lcdcc1 lcdc control register 1 r/w 0b00000000 0x0fb1 ? (disabled) ? ? 0x0fb2 lcdce1 lcdc enable register 1 r/w 0b00111110 0x0fb3 lcdce2 lcdc enable register 2 r/w 0b00000000 0x0fb4 lcdce3 lcdc enable register 3 r/w 0b00000000 0x0fb5 lcdce4 lcdc enable register 4 r/w 0b00000000 0x0fb6 lcdce5 lcdc enable register 5 r/w 0b00000000 0x0fb7 lcdce6 lcdc enable register 6 r/w 0b00000000 0x0fb8 ? (disabled) ? ? 0x0fb9 lcdcb1 lcdc blinking setting register 1 r/w 0b00000000 0x0fba lcdcb2 lcdc blinking setting register 2 r/w 0b00000000 0x0fbb, 0x0fbc ? (disabled) ? ? 0x0fbd to 0x0fd8 lcdram lcdc display ram (28 bytes) r/w 0b00000000 0x0fd9 to 0x0fe1 ? (disabled) ? ? 0x0fe2 evcr event counter control register r/w 0b00000000 0x0fe3 wcdr watch counter data register r/w 0b00111111 0x0fe4 crth main cr clock trimmi ng register (u pper) r/w 0b000xxxxx 0x0fe5 crtl main cr clock trimmi ng register (lower) r/w 0b000xxxxx 0x0fe6 sysc2 system configuratio n register 2 r/w 0b00000000 address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 50 of 172 ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. 0x0fe7 crtda main cr clock temperature dependent adjustment register r/w 0b000xxxxx 0x0fe8 sysc system configurat ion register r/w 0b00111111 0x0fe9 cmcr clock monitoring control register r/w 0b00000000 0x0fea cmdr clock monitoring data register r 0b00000000 0x0feb wdth watchdog timer selecti on id register (upper) r 0bxxxxxxxx 0x0fec wdtl watchdog timer selecti on id register (lower) r 0bxxxxxxxx 0x0fed, 0x0fee ? (disabled) ? ? 0x0fef wicr interrupt pin selection circuit control register r/w 0b01000000 0x0ff0 to 0x0fff ? (disabled) ? ? r/w : readable/writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. address register abbreviation register name r/w initial value
mb95710m series mb95770m series document number: 002-09307 rev. *d page 51 of 172 18. i/o ports (mb95710m series) ? list of port registers r/w : readable/writable (the read value is the same as the write value.) r, rm/w : readable/writable (the read value is different fr om the write value. the write value is read by the read- modify-write (rmw) type of instruction.) register name read/write initial value port 0 data register pdr0 r, rm/w 0b00000000 port 0 direction register ddr0 r/w 0b00000000 port 1 data register pdr1 r, rm/w 0b00000000 port 1 direction register ddr1 r/w 0b00000000 port 2 data register pdr2 r, rm/w 0b00000000 port 2 direction register ddr2 r/w 0b00000000 port 4 data register pdr4 r, rm/w 0b00000000 port 4 direction register ddr4 r/w 0b00000000 port 5 data register pdr5 r, rm/w 0b00000000 port 5 direction register ddr5 r/w 0b00000000 port 6 data register pdr6 r, rm/w 0b00000000 port 6 direction register ddr6 r/w 0b00000000 port 9 data register pdr9 r, rm/w 0b00000000 port 9 direction register ddr9 r/w 0b00000000 port a data register pdra r, rm/w 0b00000000 port a direction register ddra r/w 0b00000000 port b data register pdrb r, rm/w 0b00000000 port b direction register ddrb r/w 0b00000000 port c data register pdrc r, rm/w 0b00000000 port c direction register ddrc r/w 0b00000000 port e data register pdre r, rm/w 0b00000000 port e direction register ddre r/w 0b00000000 port f data register pdrf r, rm/w 0b00000000 port f direction r egister ddrf r/w 0b00000000 port g data register pdrg r, rm/w 0b00000000 port g direction register ddrg r/w 0b00000000 port 1 pull-up register pul0 r/w 0b00000000 port 2 pull-up register pul1 r/w 0b00000000 port 5 pull-up register pul5 r/w 0b00000000 port g pull-up register pulg r/w 0b00000000 a/d input disable register (lower) aidrl r/w 0b00000000
mb95710m series mb95770m series document number: 002-09307 rev. *d page 52 of 172 18.1 port 0 port 0 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.1.1 port 0 configuration port 0 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 0 data register (pdr0) ? port 0 direction register (ddr0) ? a/d input disable register (lower) (aidrl) 18.1.2 block diagrams of port 0 ? p00/int00/an00/uo2 pin this pin has the following peripheral functions: ? external interrupt input pin (int00) ? 8/12-bit a/d converter analog input pin (an00) ? uart/sio ch. 2 data output pin (uo2) ? p02/int02/an02/seg35/uck2 pin this pin has the following peripheral functions: ? external interrupt input pin (int02) ? 8/12-bit a/d converter analog input pin (an02) ? lcdc seg35 output pin (seg35) ? uart/sio ch. 2 clock i/o pin (uck2) ? p03/int03/an03/seg34/uo1 pin this pin has the following peripheral functions: ? external interrupt input pin (int03) ? 8/12-bit a/d converter analog input pin (an03) ? lcdc seg34 output pin (seg34) ? uart/sio ch. 1 data output pin (uo1) ? p05/int05/an05/seg32/uck1 pin this pin has the following peripheral functions: ? external interrupt input pin (int05) ? 8/12-bit a/d converter analog input pin (an05) ? lcdc seg32 output pin (seg32) ? uart/sio ch. 1 clock i/o pin (uck1) ? p06/int06/an06/seg31 pin this pin has the following peripheral functions: ? external interrupt input pin (int06) ? 8/12-bit a/d converter analog input pin (an06) ? lcdc seg31 output pin (seg31) ? p07/int07/an07/seg30 pin this pin has the following peripheral functions: ? external interrupt input pin (int07) ? 8/12-bit a/d converter analog input pin (an07) ? lcdc seg30 output pin (seg30)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 53 of 172 ? block diagram of p00/int00/an00/uo2, p02/int0 2/an02/seg35/uck2, p0 3/int03/an03/seg34/uo1, p05/int05/an05/seg32/uck1, p06/int06/ an06/seg31 and p07/int07/an07/seg30 ? p01/int01/an01/seg36/ui2 pin this pin has the following peripheral functions: ? external interrupt input pin (int01) ? 8/12-bit a/d converter analog input pin (an01) ? lcdc seg36 output pin (seg36) ? uart/sio ch. 2 data input pin (ui2) ? p04/int04/an04/seg33/ui1 pin this pin has the following peripheral functions: ? external interrupt input pin (int04) ? 8/12-bit a/d converter analog input pin (an04) ? lcdc seg33 output pin (seg33) ? uart/sio ch. 1 data input pin (ui1) pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write aidrl read aidrl write ddr0 aidrl 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int00, int02, int03, int05, int06 and int07) peripheral function output enable peripheral function output a/d analog input internal bus lcd output lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 54 of 172 ? block diagram of p01/int01/an01/seg36/ui2 and p04/int04/an04/seg33/ui1 18.1.3 port 0 registers ? port 0 register functions ? correspondence between registers and pins for port 0 register abbreviation data read read by read-modify-write (rmw) instruction write pdr0 0 pin state is ?l? level. pdr0 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr0 value is ?1?. as output port, outputs ?h? level. ddr0 0 port input enabled 1 port output enabled aidrl 0 analog input enabled 1 port input enabled correspondence between related register bits and pins pin name p07 p06 p05 p04 p03 p02 p01 p00 pdr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr0 aidrl pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write aidrl read aidrl write ddr0 aidrl 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int01 and int04) peripheral function output enable peripheral function output a/d analog input internal bus lcd output lcd output enable cmos
mb95710m series mb95770m series document number: 002-09307 rev. *d page 55 of 172 18.1.4 port 0 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 0 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr0 register to external pins. ? if data is written to the pdr0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr0 register returns the pdr0 register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 6 (lcdce6:seg[3 1:30]) or in the lcdc enable register 7 (lcdce7:seg[36:3 2]) to ?0? to select the gen- eral-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lc- dce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddr0 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when using an analog input shared pin as an input port, set the corresponding bit in the a/d input disable register (lower) (aidrl) to ?1?. ? if data is written to the pdr0 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr0 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr0 register, th e pdr0 register va lue is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 6 (lcdce6:seg[3 1:30]) or in the lcdc enable register 7 (lcdce7:seg[36:3 2]) to ?0? to select the gen- eral-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr0 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr0 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr0 register, the pdr0 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr0 regi ster corresponding to the input pin of a peripheral function to ?0?. ? when using the analog input shared pin as another peripheral function input pin, configure it as an input port, which is the same as the operation as an input port. ? reading the pdr0 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr0 register, the pdr0 register value is returned. ? operation as an lcdc segment output pin ? set the bit in the ddr0 register corresp onding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enable re gister 6 (lcdce6:seg[31:30]) or in the lcdc enable register 7 (lc- dce7:seg[36:32]) to ?1? to select the lcdc segment ou tput function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddr0 r egister are initialized to ?0 ? and port input is enabled . as for a pin shared with analog input, its port input is disabled becaus e the aidrl register is initialized to ?0?.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 56 of 172 ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr0 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input is enabled for the external interrupt (int00 to int07), the input is enabled and not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an analog input pin ? set the bit in the ddr0 register bit corr esponding to the analog in put pin to ?0? and the bit corresponding to that pin in the aidrl register to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? operation as an external interrupt input pin ? set the bit in the ddr0 register correspondin g to the external inte rrupt input pin to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? the pin value is always input to the external interrupt ci rcuit. when using a pin for a function other than the interrupt, disable the external interrupt fu nction corresponding to that pin. 18.2 port 1 port 1 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.2.1 port 1 configuration port 1 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 1 data register (pdr1) ? port 1 direction register (ddr1) ? port 1 pull-up register (pul1) 18.2.2 block diagrams of port 1 ? p10/ui0 pin this pin has the following peripheral function: ? uart/sio ch. 0 data input pin (ui0)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 57 of 172 ? block diagram of p10/ui0 ? p12/dbg pin this pin has the following peripheral function: ? dbg input pin (dbg) ? block diagram of p12/dbg pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable pull-up internal bus cmos pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 stop mode, watch mode (spl = 1) od hysteresis internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 58 of 172 ? p11/uo0 pin this pin has the following peripheral function: ? uart/sio ch. 0 data output pin (uo0) ?p13/adtg pin this pin has the following peripheral function: ? 8/12-bit a/d converter trigger input pin (adtg) ? p14/uck0 pin this pin has the following peripheral function: ? uart/sio ch. 0 clock i/o pin (uck0) ? p17/cmp0_o pin this pin has the following peripheral function: ? comparator ch. 0 digital output pin (cmp0_o) ? block diagram of p11/uo0, p13/ adtg, p14/uck0 and p17/cmp0_o pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output pull-up internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 59 of 172 ? p15/ppg11 pin this pin has the following peripheral function: ? 8/16-bit ppg ch. 1 output pin (ppg11) ? p16/ppg10 pin this pin has the following peripheral function: ? 8/16-bit ppg ch. 1 output pin (ppg10) ? block diagram of p15/ppg11 and p16/ppg10 18.2.3 port 1 registers ? port 1 register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port 1 register abbreviation data read read by read-modify-write (rmw) instruction write pdr1 0 pin state is ?l? level. pdr1 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr1 value is ?1?. as output port, outputs ?h? level.* ddr1 0 port input enabled 1 port output enabled pul1 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name p17 p16 p15 p14 p13 p12 p11 p10 pdr1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr1 pul1 - - - pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 60 of 172 18.2.4 port 1 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 1 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr1 register to external pins. ? if data is written to the pdr1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr1 register returns the pdr1 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr1 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr1 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr1 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr1 register, th e pdr1 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr1 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr1 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr1 register, the pdr1 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr1 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr1 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr1 register, the pdr1 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr1 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr1 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input of p10/ui0 and p14/uck0 is e nabled by the external interrupt control register ch. 0 (eic00) of the external interr upt circuit and the interrupt pin selection circ uit control register (wicr) of the interrupt pin selection circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul1 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul1 register.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 61 of 172 18.3 port 2 port 2 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.3.1 port 2 configuration port 2 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 2 data register (pdr2) ? port 2 direction register (ddr2) ? port 2 pull-up register (pul2) 18.3.2 block diagrams of port 2 ? p20/ppg00/cmp0_n pin this pin has the following peripheral functions: ? 8/16-bit ppg ch. 0 output pin (ppg00) ? comparator ch. 0 inverting analog input (negative input) pin (cmp0_n) ? p21/ppg01/cmp0_p pin this pin has the following peripheral functions: ? 8/16-bit ppg ch. 0 output pin (ppg01) ? comparator ch. 0 non-inverting analog input (positive input) pin (cmp0_p) ? block diagram of p20/ppg00/cmp0_n and p21/ppg01/cmp0_p pdr2 pin pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write pul2 read pul2 write ddr2 pul2 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output pull-up internal bus analog input analog input enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 62 of 172 ?p22/scl pin this pin has the following peripheral function: ?i 2 c bus interface ch. 0 clock i/o pin (scl) ? p23/sda pin this pin has the following peripheral function: ?i 2 c bus interface ch. 0 data i/o pin (sda) ? block diagram of p22/scl and p23/sda 18.3.3 port 2 registers ? port 2 register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port 2 register abbreviation data read read by read-modify-write (rmw) instruction write pdr2 0 pin state is ?l? level. pdr2 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr2 value is ?1?. as output port, outputs ?h? level.* ddr2 0 port input enabled 1 port output enabled pul2 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name----p23p22p21p20 pdr2 ---- bit3 bit2 bit1 bit0 ddr2 pul2 - - pdr2 pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write ddr2 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output cmos pin od internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 63 of 172 18.3.4 port 2 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 2 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr2 register to external pins. ? if data is written to the pdr2 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr2 register returns the pdr2 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr2 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr2 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr2 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr2 register, th e pdr2 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr2 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr2 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr2 register, the pdr2 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr2 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr2 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr2 register, the pdr2 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr2 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr2 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul2 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul2 register. ? operation as a comparator input pin ? regardless of the value of t he pdr2 register and that of the ddr2 regist er, if the comparator analog input enable bit in the comparator control register ch. 0 (cmr0:vcid) is set to ?0?, the comparator input function is enabled. ? to disable the comparator input function, set the vcid bit to ?1?. ? for details of the comparator, refer to ?chapter 29 comparator? in ?new 8fx mb95710m/770m series hard- ware manual?.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 64 of 172 18.4 port 4 port 4 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.4.1 port 4 configuration port 4 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 4 data register (pdr4) ? port 4 direction register (ddr4) 18.4.2 block diagrams of port 4 ? p40/seg21 pin this pin has the following peripheral function: ? lcdc seg21 output pin (seg21) ? p41/seg20 pin this pin has the following peripheral function: ? lcdc seg20 output pin (seg20) ? p42/seg19 pin this pin has the following peripheral function: ? lcdc seg19 output pin (seg19) ? p43/seg18 pin this pin has the following peripheral function: ? lcdc seg18 output pin (seg18) ? block diagram of p40/seg21, p41/ seg20, p42/seg19 and p43/seg18 pdr4 pin pdr4 read pdr4 write executing bit manipulation instruction ddr4 read ddr4 write ddr4 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 65 of 172 18.4.3 port 4 registers ? port 4 register functions ? correspondence between registers and pins for port 4 18.4.4 port 4 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 4 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr4 register to external pins. ? if data is written to the pdr4 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr4 register returns the pdr4 register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 5 (lcdce5:seg[21:18]) to ?0? to select the general -purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lcdce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddr4 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr4 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr4 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr4 register, th e pdr4 register va lue is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 5 (lcdce5:seg[21 :18]) to ?0? to select the general-purpose i/o port function, and th en set the pictl bit in the lcdce1 re gister to ?1?. ? operation as an lcdc segment output pin ? set the bit in the ddr4 register corresp onding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enabl e register 5 (lcdce5:seg[21:18]) to ?1? to select the lcdc segment output function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddr4 register are initialized to ?0? and port input is enabled. register abbreviation data read read by read-modify-write (rmw) instruction write pdr4 0 pin state is ?l? level. pdr4 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr4 value is ?1?. as output port, outputs ?h? level. ddr4 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name----p43p42p41p40 pdr4 ----bit3bit2bit1bit0 ddr4
mb95710m series mb95770m series document number: 002-09307 rev. *d page 66 of 172 ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr4 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. 18.5 port 5 port 5 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.5.1 port 5 configuration port 5 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 5 data register (pdr5) ? port 5 direction register (ddr5) ? port 5 pull-up register (pul5) 18.5.2 block diagrams of port 5 ? p50/to01 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 0 output pin (to01) ? p51/ec0 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 0 clock input pin (ec0) ? p52/ti0/to00 pin this pin has the following peripheral functions: ? 16-bit reload timer ch. 0 input pin (ti0) ? 8/16-bit composite timer ch. 0 output pin (to00) ? p53/to0 pin this pin has the following peripheral function: ? 16-bit reload timer ch. 0 output pin (to0)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 67 of 172 ? block diagram of p50/to01, p51/ec0, p52/ti0/to00 and p53/to0 18.5.3 port 5 registers ? port 5 register functions ? correspondence between registers and pins for port 5 register abbreviation data read read by read-modify-write (rmw) instruction write pdr5 0 pin state is ?l? level. pdr5 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr5 value is ?1?. as output port, outputs ?h? level. ddr5 0 port input enabled 1 port output enabled pul5 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name----p53p52p51p50 pdr5 ----bit3bit2bit1bit0 ddr5 pul5 pdr5 pin pdr5 read pdr5 write executing bit manipulation instruction ddr5 read ddr5 write pul5 read pul5 write ddr5 pul5 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output pull-up internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 68 of 172 18.5.4 port 5 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 5 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr5 register to external pins. ? if data is written to the pdr5 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr5 register returns the pdr5 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr5 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr5 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr5 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr5 register, th e pdr5 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr5 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr5 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr5 register, the pdr5 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr5 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr5 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr5 register, the pdr5 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr5 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr5 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul5 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul5 register.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 69 of 172 18.6 port 6 port 6 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.6.1 port 6 configuration port 6 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 6 data register (pdr6) ? port 6 direction register (ddr6) 18.6.2 block diagrams of port 6 ? p60/seg10 pin this pin has the following peripheral function: ? lcdc seg10 output pin (seg10) ? p61/seg11 pin this pin has the following peripheral function: ? lcdc seg11 output pin (seg11) ? p62/seg12 pin this pin has the following peripheral function: ? lcdc seg12 output pin (seg12) ? p63/seg13 pin this pin has the following peripheral function: ? lcdc seg13 output pin (seg13) ? p64/seg14 pin this pin has the following peripheral function: ? lcdc seg14 output pin (seg14) ? p65/seg15 pin this pin has the following peripheral function: ? lcdc seg15 output pin (seg15) ? p66/seg16 pin this pin has the following peripheral function: ? lcdc seg16 output pin (seg16) ? p67/seg17 pin this pin has the following peripheral function: ? lcdc seg17 output pin (seg17)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 70 of 172 ? block diagram of p60/seg10, p61/seg11, p62/seg 12, p63/seg13, p64/seg14, p65/seg15, p66/seg16 and p67/seg17 18.6.3 port 6 registers ? port 6 register functions ? correspondence between registers and pins for port 6 register abbreviation data read read by read-modify-write (rmw) instruction write pdr6 0 pin state is ?l? level. pdr6 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr6 value is ?1?. as output port, outputs ?h? level. ddr6 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name p67 p66 p65 p64 p63 p62 p61 p60 pdr6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr6 pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write ddr6 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 71 of 172 18.6.4 port 6 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 6 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr6 register to external pins. ? if data is written to the pdr6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr6 register returns the pdr6 register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 4 (lcdce4:seg[1 5:10]) or in the lcdc enable register 5 (lcdce5:seg[17:1 6]) to ?0? to select the gen- eral-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lc- dce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddr6 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr6 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr6 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr6 register, th e pdr6 register va lue is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 4 (lcdce4:seg[1 5:10]) or in the lcdc enable register 5 (lcdce5:seg[17:1 6]) to ?0? to select the gen- eral-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as an lcdc segment output pin ? set the bit in the ddr6 register corresp onding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enable re gister 4 (lcdce4:seg[15:10]) or in the lcdc enable register 5 (lc- dce5:seg[17:16]) to ?1? to select the lcdc segment ou tput function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddr6 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr6 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 72 of 172 18.7 port 9 port 9 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.7.1 port 9 configuration port 9 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 9 data register (pdr9) ? port 9 direction register (ddr9) 18.7.2 block diagrams of port 9 ? p90/v4 pin this pin has the following peripheral function: ? lcd drive power supply pin (v4) ? p91/v3 pin this pin has the following peripheral function: ? lcd drive power supply pin (v3) ? p92/v2 pin this pin has the following peripheral function: ? lcd drive power supply pin (v2) ? p93/v1 pin this pin has the following peripheral function: ? lcd drive power supply pin (v1) ? p94/v0 pin this pin has the following peripheral function: ? lcd drive power supply pin (v0) ? block diagram of p90/v4, p91/ v3, p92/v2, p93/v1 and p94/v0 pdr9 pin pdr9 read pdr9 write executing bit manipulation instruction ddr9 read ddr9 write ddr9 0 1 stop mode, watch mode (spl = 1) lcd power supply lcd power supply enable internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 73 of 172 18.7.3 port 9 registers ? port 9 register functions ? correspondence between registers and pins for port 9 18.7.4 port 9 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 9 register corresponding to that pin is set to ?1?. ? when a pin is used as an output port, it outputs the value of the pdr9 register to external pins. ? if data is written to the pdr9 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr9 register returns the pdr9 register value. ? to use a pin shared with the lcdc as an output port, set th e bit corresponding to that pin in the ve[4:0] bits in the lcdc enable register 1 (lcdce1) to ?0? to select the general-purpose i/o port function. ? operation as an input port ? a pin becomes an input port if the bit in the ddr9 register corresponding to that pin is set to ?0?. ? if data is written to the pdr9 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr9 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr9 register, th e pdr9 register va lue is returned. ? to use a pin shared with the lcdc as an input port, set the bit corresponding to that pin in the ve[4:0] bits in the lcdce1 register to ?0? to select the general-purpose i/o port function. ? operation at reset if the cpu is reset, all bits in the ddr9 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr9 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an lcd drive power supply pin ? set the bit in the ddr9 register corresponding to an lcd drive power supply pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcd drive power supply pin, set the bit corresponding to that pin in the ve[ 4:0] bits in the lcdce1 regi ster to ?1? to select the lcd drive power supply function. register abbreviation data read read by read-modify-write (rmw) instruction write pdr9 0 pin state is ?l? level. pdr9 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr9 value is ?1?. as output port, outputs ?h? level. ddr9 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name - - - p94 p93 p92 p91 p90 pdr9 - - - bit4 bit3 bit2 bit1 bit0 ddr9
mb95710m series mb95770m series document number: 002-09307 rev. *d page 74 of 172 18.8 port a port a is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.8.1 port a configuration port a is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port a data register (pdra) ? port a direction register (ddra) 18.8.2 block diagrams of port a ? pa0/com0 pin this pin has the following peripheral function: ? lcdc com0 output pin (com0) ? pa1/com1 pin this pin has the following peripheral function: ? lcdc com1 output pin (com1) ? pa2/com2 pin this pin has the following peripheral function: ? lcdc com2 output pin (com2) ? pa3/com3 pin this pin has the following peripheral function: ? lcdc com3 output pin (com3) ? pa4/com4 pin this pin has the following peripheral function: ? lcdc com4 output pin (com4) ? pa5/com5 pin this pin has the following peripheral function: ? lcdc com5 output pin (com5) ? pa6/com6 pin this pin has the following peripheral function: ? lcdc com6 output pin (com6) ? pa7/com7 pin this pin has the following peripheral function: ? lcdc com7 output pin (com7)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 75 of 172 ? block diagram of pa0/com0, pa1/com1, pa2/com2 , pa3/com3, pa4/com4, pa5/com5, pa6/com6 and pa7/com7 18.8.3 port a registers ? port a register functions ? correspondence between registers and pins for port a register abbreviation data read read by read-modify-write (rmw) instruction write pdra 0 pin state is ?l? level. pdra value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdra value is ?1?. as output port, outputs ?h? level. ddra 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pdra bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddra pdra pin pdra read pdra write executing bit manipulation instruction ddra read ddra write ddra 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 76 of 172 18.8.4 port a operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr a register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdra register to external pins. ? if data is written to the pdra register, the value is stored in the output latch and is outpu t to the pin set as an output port as it is. ? reading the pdra register returns the pdra register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 2 (lcdce2:com[7:0]) to ?0? to select the general-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lcdce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddra register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdra register, the value is stor ed in the output latch but is not output to the pin set as an input port. ? reading the pdra register returns the pin value. howeve r, if the read-modify-write (rmw) type of instruction is used to read the pdra register, the pdra register value is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 2 (lcdce2:com[7:0]) to ?0? to select the general-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as an lcdc common output pin ? set the bit in the ddra register corresponding to an lcdc common output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc common output pin, set a corresponding function select bit in the lcdc enable register 2 (lcdce2:com[7: 0]) to ?1? to select the l cdc common outp ut function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddra register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddra reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 77 of 172 18.9 port b port b is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.9.1 port b configuration port b is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port b data register (pdrb) ? port b direction register (ddrb) 18.9.2 block diagrams of port b ? pb0/seg00 pin this pin has the following peripheral function: ? lcdc seg00 output pin (seg00) ? pb1/seg01 pin this pin has the following peripheral function: ? lcdc seg01 output pin (seg01) ? pb2/seg37 pin this pin has the following peripheral function: ? lcdc seg37 output pin (seg37) ? pb3/seg38 pin this pin has the following peripheral function: ? lcdc seg38 output pin (seg38) ? pb4/seg39 pin this pin has the following peripheral function: ? lcdc seg39 output pin (seg39) ? block diagram of pb0/seg 00, pb1/seg01, pb2/seg37, pb3/seg38 and pb4/seg39 pdrb pin pdrb read pdrb write executing bit manipulation instruction ddrb read ddrb write ddrb 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 78 of 172 18.9.3 port b registers ? port b register functions ? correspondence between registers and pins for port b 18.9.4 port b operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr b register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrb register to external pins. ? if data is written to the pdrb register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrb register returns the pdrb register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 3 (lcdce3:seg[0 1:00]) or in the lcdc enable register 7 (lcdce7:seg[39:3 7]) to ?0? to select the gen- eral-purpose i/o port function, and t hen set the port input control bit (pic tl) in the lcdc enab le register 1 (lc- dce1) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddrb register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrb register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrb register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdrb register, th e pdrb register value is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 3 (lcdce3:seg[0 1:00]) or in the lcdc enable register 7 (lcdce7:seg[39:3 7]) to ?0? to select the gen- eral-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as an lcdc segment output pin ? set the bit in the ddrb register correspo nding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enable re gister 3 (lcdce3:seg[01:00]) or in the lcdc enable register 7 (lc- dce7:seg[39:37]) to ?1? to select the lcdc segment ou tput function, and then set the pictl bit in the lcdce1 register to ?1?. register abbreviation data read read by read-modify-write (rmw) instruction write pdrb 0 pin state is ?l? level. pdrb value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrb value is ?1?. as output port, outputs ?h? level. ddrb 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name - - - pb4 pb3 pb2 pb1 pb0 pdrb - - - bit4 bit3 bit2 bit1 bit0 ddrb
mb95710m series mb95770m series document number: 002-09307 rev. *d page 79 of 172 ? operation at reset if the cpu is reset, all bits in the ddrb register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to en ter the high impedance state regardless of the ddrb reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. 18.10 port c port c is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.10.1 port c configuration port c is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port c data register (pdrc) ? port c direction register (ddrc) 18.10.2 block diagrams of port c ?pc0/seg02 pin this pin has the following peripheral function: ? lcdc seg02 output pin (seg02) ?pc1/seg03 pin this pin has the following peripheral function: ? lcdc seg03 output pin (seg03) ?pc2/seg04 pin this pin has the following peripheral function: ? lcdc seg04 output pin (seg04) ?pc3/seg05 pin this pin has the following peripheral function: ? lcdc seg05 output pin (seg05) ?pc4/seg06 pin this pin has the following peripheral function: ? lcdc seg06 output pin (seg06) ?pc5/seg07 pin this pin has the following peripheral function: ? lcdc seg07 output pin (seg07) ?pc6/seg08 pin this pin has the following peripheral function: ? lcdc seg08 output pin (seg08) ?pc7/seg09 pin this pin has the following peripheral function: ? lcdc seg09 output pin (seg09)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 80 of 172 ? block diagram of pc0/seg02, pc1/seg 03, pc2/seg04, pc3/seg05, pc4/se g06, pc5/seg07, pc6/seg08 and pc7/seg09 18.10.3 port c registers ? port c register functions ? correspondence between registers and pins for port c register abbreviation data read read by read-modify-write (rmw) instruction write pdrc 0 pin state is ?l? level. pdrc value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrc value is ?1?. as output port, outputs ?h? level. ddrc 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pdrc bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddrc pdrc pin pdrc read pdrc write executing bit manipulation instruction ddrc read ddrc write ddrc 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 81 of 172 18.10.4 port c operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr c register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrc register to external pins. ? if data is written to the pdrc register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrc register returns the pdrc register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 3 (lcdce3:seg[0 7:02]) or in the lcdc enable register 4 (lcdce4:seg[09:0 8]) to ?0? to select the gen- eral-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lc- dce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddrc register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrc register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrc register returns the pin value. however, if the read-modif y-write (rmw) type of instruction is used to read the pdrc register, th e pdrc register value is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 3 (lcdce3:seg[0 7:02]) or in the lcdc enable register 4 (lcdce4:seg[09:0 8]) to ?0? to select the gen- eral-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as an lcdc segment output pin ? set the bit in the ddrc register correspondi ng to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enable re gister 3 (lcdce3:seg[07:02]) or in the lcdc enable register 4 (lc- dce4:seg[09:08]) to ?1? to select the lcdc segment ou tput function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddrc register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to en ter the high impedance state regardless of the ddrc reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 82 of 172 18.11 port e port e is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.11.1 port e configuration port e is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port e data register (pdre) ? port e direction register (ddre) 18.11.2 block diagrams of port e ? pe0/seg22 pin this pin has the following peripheral function: ? lcdc seg22 output pin (seg22) ? pe1/seg23 pin this pin has the following peripheral function: ? lcdc seg23 output pin (seg23) ? pe2/seg24 pin this pin has the following peripheral function: ? lcdc seg24 output pin (seg24) ? pe3/seg25 pin this pin has the following peripheral function: ? lcdc seg25 output pin (seg25) ? pe4/seg26 pin this pin has the following peripheral function: ? lcdc seg26 output pin (seg26) ? block diagram of pe0/seg 22, pe1/seg23, pe2/seg24, pe3/seg25 and pe4/seg26 pdre pin pdre read pdre write executing bit manipulation instruction ddre read ddre write ddre 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 83 of 172 ? pe5/seg27/to11 pin this pin has the following peripheral functions: ? lcdc seg27 output pin (seg27) ? 8/16-bit composite timer ch. 1 output pin (to11) ? pe6/seg28/to10 pin this pin has the following peripheral functions: ? lcdc seg28 output pin (seg28) ? 8/16-bit composite timer ch. 1 output pin (to10) ? pe7/seg29/ec1 pin this pin has the following peripheral functions: ? lcdc seg29 output pin (seg29) ? 8/16-bit composite timer ch. 1 clock input pin (ec1) ? block diagram of pe5/seg27/to11, pe6/seg28/to10 and pe7/seg29/ec1 18.11.3 port e registers ? port e register functions ? correspondence between registers and pins for port e register abbreviation data read read by read-modify-write (rmw) instruction write pdre 0 pin state is ?l? level. pdre value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdre value is ?1?. as output port, outputs ?h? level. ddre 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pdre bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddre pdre pin pdre read pdre write executing bit manipulation instruction ddre read ddre write ddre 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 84 of 172 18.11.4 port e operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr e register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdre register to external pins. ? if data is written to the pdre register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdre register returns the pdre register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 5 (lcdce5:seg[2 3:22]) or in the lcdc enable register 6 (lcdce6:seg[29:2 4]) to ?0? to select the gen- eral-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lc- dce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddre register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdre register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdre register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdre register, th e pdre register value is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 5 (lcdce5:seg[2 3:22]) or in the lcdc enable register 6 (lcdce6:seg[29:2 4]) to ?0? to select the gen- eral-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdre register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdre register. however, if the read- modify-write (rmw) type of instruction is used to read the pdre register, the pdre register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddre regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdre register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. however, if the re ad-modify-write (rmw) type of instruction is used to read the pdre register, the pdre register value is returned. ? operation as an lcdc segment output pin ? set the bit in the ddre register correspo nding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enable re gister 5 (lcdce5:seg[23:22]) or in the lcdc enable register 6 (lc- dce6:seg[29:24]) to ?1? to select the lcdc segment ou tput function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddre register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to en ter the high impedance state regardless of the ddre reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 85 of 172 ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. 18.12 port f port f is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.12.1 port f configuration port f is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port f data register (pdrf) ? port f direction register (ddrf) 18.12.2 block diagrams of port f ?pf0/x0 pin this pin has the following peripheral function: ? main clock input oscillation pin (x0) ?pf1/x1 pin this pin has the following peripheral function: ? main clock i/o oscillation pin (x1) ? block diagram of pf0/x0 and pf1/x1 pdrf pin pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 stop mode, watch mode (spl = 1) internal bus hysteresis
mb95710m series mb95770m series document number: 002-09307 rev. *d page 86 of 172 ?pf2/rst pin this pin has the following peripheral function: ? reset pin (rst ) ? block diagram of pf2/rst 18.12.3 port f registers ? port f register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port f *: pf2/rst is the dedicated reset pin on mb95f714m/f716m/f718m. register abbreviation data read read by read-modify-write (rmw) instruction write pdrf 0 pin state is ?l? level. pdrf value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrf value is ?1?. as output port, outputs ?h? level.* ddrf 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name-----pf2 * pf1 pf0 pdrf -----bit2bit1bit0 ddrf pdrf pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 1 0 stop mode, watch mode (spl = 1) reset input reset input enable reset output enable reset output pin od internal bus hysteresis
mb95710m series mb95770m series document number: 002-09307 rev. *d page 87 of 172 18.12.4 port f operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr f register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrf register to external pins. ? if data is written to the pdrf register, the value is stored in the output latch and is outpu t to the pin set as an output port as it is. ? reading the pdrf register returns the pdrf register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddrf register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrf register , the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrf register returns the pin value. howeve r, if the read-modify-write (rmw) type of instruction is used to read the pdrf register, t he pdrf register value is returned. ? operation at reset if the cpu is reset, all bits in the ddrf register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddrf reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. 18.13 port g port g is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 18.13.1 port g configuration port g is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port g data register (pdrg) ? port g direction register (ddrg) ? port g pull-up register (pulg) 18.13.2 block diagram of port g ? pg1/x0a pin this pin has the following peripheral function: ? subclock input oscillation pin (x0a) ? pg2/x1a pin this pin has the following peripheral function: ? subclock i/o oscillation pin (x1a)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 88 of 172 ? block diagram of pg1/x0a and pg2/x1a 18.13.3 port g registers ? port g register functions ? correspondence between registers and pins for port g register abbreviation data read read by read-modify-write (rmw) instruction write pdrg 0 pin state is ?l? level. pdrg value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrg value is ?1?. as output port, outputs ?h? level. ddrg 0 port input enabled 1 port output enabled pulg 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name-----pg2pg1- pdrg -----bit2bit1- ddrg pulg pdrg pin pdrg read pdrg write executing bit manipulation instruction ddrg read ddrg write pulg read pulg write ddrg pulg 0 1 stop mode, watch mode (spl = 1) hysteresis pull-up internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 89 of 172 18.13.4 port g operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr g register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrg regi ster to external pins. ? if data is written to the pdrg register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrg register returns the pdrg register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddrg register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrg register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrg register returns the pin value. however, if the read-modify-write (rmw) type of instruction is used to read the pdrg register, th e pdrg register va lue is returned. ? operation at reset if the cpu is reset, all bits in the ddrg register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is comp ulsorily made to enter th e high impedance state regardless of the ddrg reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pulg register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pulg register.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 90 of 172 19. i/o ports (mb95770m series) ? list of port registers r/w : readable/writable (the read value is the same as the write value.) r, rm/w : readable/writable (the read value is different fr om the write value. the write value is read by the read- modify-write (rmw) type of instruction.) register name read/write initial value port 0 data register pdr0 r, rm/w 0b00000000 port 0 direction register ddr0 r/w 0b00000000 port 1 data register pdr1 r, rm/w 0b00000000 port 1 direction register ddr1 r/w 0b00000000 port 2 data register pdr2 r, rm/w 0b00000000 port 2 direction register ddr2 r/w 0b00000000 port 6 data register pdr6 r, rm/w 0b00000000 port 6 direction register ddr6 r/w 0b00000000 port 9 data register pdr9 r, rm/w 0b00000000 port 9 direction register ddr9 r/w 0b00000000 port a data register pdra r, rm/w 0b00000000 port a direction register ddra r/w 0b00000000 port b data register pdrb r, rm/w 0b00000000 port b direction register ddrb r/w 0b00000000 port c data register pdrc r, rm/w 0b00000000 port c direction register ddrc r/w 0b00000000 port e data register pdre r, rm/w 0b00000000 port e direction register ddre r/w 0b00000000 port f data register pdrf r, rm/w 0b00000000 port f direction r egister ddrf r/w 0b00000000 port g data register pdrg r, rm/w 0b00000000 port g direction register ddrg r/w 0b00000000 port 1 pull-up register pul1 r/w 0b00000000 port 2 pull-up register pul2 r/w 0b00000000 port g pull-up register pulg r/w 0b00000000 a/d input disable register (lower) aidrl r/w 0b00000000
mb95710m series mb95770m series document number: 002-09307 rev. *d page 91 of 172 19.1 port 0 port 0 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.1.1 port 0 configuration port 0 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 0 data register (pdr0) ? port 0 direction register (ddr0) ? a/d input disable register (lower) (aidrl) 19.1.2 block diagrams of port 0 ? p00/int00/an00/seg29/uo2 pin this pin has the following peripheral functions: ? external interrupt input pin (int00) ? 8/12-bit a/d converter analog input pin (an00) ? lcdc seg29 output pin (seg29) ? uart/sio ch. 2 data output pin (uo2) ? p02/int02/an02/seg27/uck2 pin this pin has the following peripheral functions: ? external interrupt input pin (int02) ? 8/12-bit a/d converter analog input pin (an02) ? lcdc seg27 output pin (seg27) ? uart/sio ch. 2 clock i/o pin (uck2) ? p03/int03/an03/seg26/uo1 pin this pin has the following peripheral functions: ? external interrupt input pin (int03) ? 8/12-bit a/d converter analog input pin (an03) ? lcdc seg26 output pin (seg26) ? uart/sio ch. 1 data output pin (uo1) ? p05/int05/an05/seg24/uck1 pin this pin has the following peripheral functions: ? external interrupt input pin (int05) ? 8/12-bit a/d converter analog input pin (an05) ? lcdc seg24 output pin (seg24) ? uart/sio ch. 1 clock i/o pin (uck1) ? p06/int06/an06/seg23 pin this pin has the following peripheral functions: ? external interrupt input pin (int06) ? 8/12-bit a/d converter analog input pin (an06) ? lcdc seg23 output pin (seg23) ? p07/int07/an07/seg22 pin this pin has the following peripheral functions: ? external interrupt input pin (int07) ? 8/12-bit a/d converter analog input pin (an07) ? lcdc seg22 output pin (seg22)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 92 of 172 ? block diagram of p00/int00/an00/seg29/uo2, p02/int02/an02/seg27/uck2, p03/int03/an03/seg26/ uo1, p05/int05/an05/seg24/ uck1, p06/int06/an06/seg23 and p07/int07/an07/seg22 ? p01/int01/an01/seg28/to00/ui2 pin this pin has the following peripheral functions: ? external interrupt input pin (int01) ? 8/12-bit a/d converter analog input pin (an01) ? lcdc seg28 output pin (seg28) ? 8/16-bit composite timer ch. 0 output pin (to00) ? uart/sio ch. 2 data input pin (ui2) ? p04/int04/an04/seg25/ui1 pin this pin has the following peripheral functions: ? external interrupt input pin (int04) ? 8/12-bit a/d converter analog input pin (an04) ? lcdc seg25 output pin (seg25) ? uart/sio ch. 1 data input pin (ui1) pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write aidrl read aidrl write ddr0 aidrl 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int00, int02, int03, int05, int06 and int07) peripheral function output enable peripheral function output a/d analog input internal bus lcd output lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 93 of 172 ? block diagram of p01/int01/an01/seg28 /to00/ui2 and p04/int04/an04/seg25/ui1 19.1.3 port 0 registers ? port 0 register functions ? correspondence between registers and pins for port 0 register abbreviation data read read by read-modify-write (rmw) instruction write pdr0 0 pin state is ?l? level. pdr0 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr0 value is ?1?. as output port, outputs ?h? level. ddr0 0 port input enabled 1 port output enabled aidrl 0 analog input enabled 1 port input enabled correspondence between related register bits and pins pin name p07 p06 p05 p04 p03 p02 p01 p00 pdr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr0 aidrl pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write aidrl read aidrl write ddr0 aidrl 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int01 and int04) peripheral function output enable peripheral function output a/d analog input internal bus lcd output lcd output enable cmos
mb95710m series mb95770m series document number: 002-09307 rev. *d page 94 of 172 19.1.4 port 0 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 0 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr0 register to external pins. ? if data is written to the pdr0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr0 register returns the pdr0 register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 5 (lcdce5:seg[2 3:22]) or in the lcdc enable register 6 (lcdce6:seg[29:2 4]) to ?0? to select the gen- eral-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lc- dce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddr0 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when using an analog input shared pin as an input port, set the corresponding bit in the a/d input disable register (lower) (aidrl) to ?1?. ? if data is written to the pdr0 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr0 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr0 register, th e pdr0 register va lue is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 5 (lcdce5:seg[2 3:22]) or in the lcdc enable register 6 (lcdce6:seg[29:2 4]) to ?0? to select the gen- eral-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr0 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr0 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr0 register, the pdr0 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr0 regi ster corresponding to the input pin of a peripheral function to ?0?. ? when using the analog input shared pin as another peripheral function input pin, configure it as an input port, which is the same as the operation as an input port. ? reading the pdr0 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr0 register, the pdr0 register value is returned. ? operation as an lcdc segment output pin ? set the bit in the ddr0 register corresp onding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enable re gister 5 (lcdce5:seg[23:22]) or in the lcdc enable register 6 (lc- dce6:seg[29:24]) to ?1? to select the lcdc segment ou tput function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddr0 r egister are initialized to ?0 ? and port input is enabled . as for a pin shared with analog input, its port input is disabled becaus e the aidrl register is initialized to ?0?.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 95 of 172 ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr0 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input is enabled for the external interrupt (int00 to int07), the input is enabled and not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an analog input pin ? set the bit in the ddr0 register bit corr esponding to the analog in put pin to ?0? and the bit corresponding to that pin in the aidrl register to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? operation as an external interrupt input pin ? set the bit in the ddr0 register correspondin g to the external inte rrupt input pin to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? the pin value is always input to the external interrupt ci rcuit. when using a pin for a function other than the interrupt, disable the external interrupt fu nction corresponding to that pin. 19.2 port 1 port 1 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.2.1 port 1 configuration port 1 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 1 data register (pdr1) ? port 1 direction register (ddr1) ? port 1 pull-up register (pul1) 19.2.2 block diagrams of port 1 ? p10/ui0/to0 pin this pin has the following peripheral functions: ? uart/sio ch. 0 data input pin (ui0) ? 16-bit reload timer ch. 0 output pin (to0)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 96 of 172 ? block diagram of p10/ui0/to0 ? p12/dbg pin this pin has the following peripheral function: ? dbg input pin (dbg) ? block diagram of p12/dbg pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output pull-up internal bus cmos pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 stop mode, watch mode (spl = 1) od hysteresis internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 97 of 172 ? p11/uo0 pin this pin has the following peripheral function: ? uart/sio ch. 0 data output pin (uo0) ? p13/adtg/to01 pin this pin has the following peripheral functions: ? 8/12-bit a/d converter trigger input pin (adtg) ? 8/16-bit composite timer ch. 0 output pin (to01) ? p14/uck0/ec0/ti0 pin this pin has the following peripheral functions: ? uart/sio ch. 0 clock i/o pin (uck0) ? 8/16-bit composite timer ch. 0 clock input pin (ec0) ? 16-bit reload timer ch. 0 input pin (ti0) ? p17/cmp0_o pin this pin has the following peripheral function: ? comparator ch. 0 digital output pin (cmp0_o) ? block diagram of p11/uo0, p13/adtg/t o01, p14/uck0/ec0/ti0 and p17/cmp0_o pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output pull-up internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 98 of 172 ? p15/seg31/ppg11 pin this pin has the following peripheral functions: ? lcdc seg31 output pin (seg31) ? 8/16-bit ppg ch. 1 output pin (ppg11) ? p16/seg30/ppg10 pin this pin has the following peripheral functions: ? lcdc seg30 output pin (seg30) ? 8/16-bit ppg ch. 1 output pin (ppg10) ? block diagram of p15/seg31/ ppg11 and p16/seg30/ppg10 19.2.3 port 1 registers ? port 1 register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port 1 register abbreviation data read read by read-modify-write (rmw) instruction write pdr1 0 pin state is ?l? level. pdr1 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr1 value is ?1?. as output port, outputs ?h? level.* ddr1 0 port input enabled 1 port output enabled pul1 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name p17 p16 p15 p14 p13 p12 p11 p10 pdr1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr1 pul1 - - - pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 99 of 172 19.2.4 port 1 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 1 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr1 register to external pins. ? if data is written to the pdr1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr1 register returns the pdr1 register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 6 (lcdce6:seg[31:30]) to ?0? to select the general -purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lcdce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddr1 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr1 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr1 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr1 register, th e pdr1 register va lue is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 6 (lcdce6:seg[31 :30]) to ?0? to select the general-purpose i/o port function, and th en set the pictl bit in the lcdce1 re gister to ?1?. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr1 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr1 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr1 register, the pdr1 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr1 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr1 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr1 register, the pdr1 register value is returned. ? operation as an lcdc segment output pin ? set the bit in the ddr1 register corresp onding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enabl e register 6 (lcdce6:seg[31:30]) to ?1? to select the lcdc segment output function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddr1 register are initialized to ?0? and port input is enabled.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 100 of 172 ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr1 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input of p10/ui0/to0 and p14/uck0 /ec0/ti0 is enabled by the external interrupt control register ch. 0 (eic00) of the external interrupt circuit an d the interrupt pin selection circuit control register (wicr) of the interrupt pin selection circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul1 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul1 register. 19.3 port 2 port 2 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.3.1 port 2 configuration port 2 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 2 data register (pdr2) ? port 2 direction register (ddr2) ? port 2 pull-up register (pul2) 19.3.2 block diagrams of port 2 ? p20/ppg00/cmp0_n pin this pin has the following peripheral functions: ? 8/16-bit ppg ch. 0 output pin (ppg00) ? comparator ch. 0 inverting analog input (negative input) pin (cmp0_n) ? p21/ppg01/cmp0_p pin this pin has the following peripheral functions: ? 8/16-bit ppg ch. 0 output pin (ppg01) ? comparator ch. 0 non-inverting analog input (positive input) pin (cmp0_p)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 101 of 172 ? block diagram of p20/ppg00/cmp0_n and p21/ppg01/cmp0_p ?p22/scl pin this pin has the following peripheral function: ?i 2 c bus interface ch. 0 clock i/o pin (scl) ? p23/sda pin this pin has the following peripheral function: ?i 2 c bus interface ch. 0 data i/o pin (sda) ? block diagram of p22/scl and p23/sda pdr2 pin pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write pul2 read pul2 write ddr2 pul2 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output pull-up internal bus analog input analog input enable pdr2 pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write ddr2 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output cmos pin od internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 102 of 172 19.3.3 port 2 registers ? port 2 register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port 2 19.3.4 port 2 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 2 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr2 register to external pins. ? if data is written to the pdr2 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr2 register returns the pdr2 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr2 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr2 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr2 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr2 register, th e pdr2 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr2 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr2 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr2 register, the pdr2 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr2 regi ster corresponding to the input pin of a peripheral function to ?0?. register abbreviation data read read by read-modify-write (rmw) instruction write pdr2 0 pin state is ?l? level. pdr2 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr2 value is ?1?. as output port, outputs ?h? level.* ddr2 0 port input enabled 1 port output enabled pul2 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name----p23p22p21p20 pdr2 ---- bit3 bit2 bit1 bit0 ddr2 pul2 - -
mb95710m series mb95770m series document number: 002-09307 rev. *d page 103 of 172 ? reading the pdr2 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr2 register, the pdr2 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr2 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr2 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul2 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul2 register. ? operation as a comparator input pin ? regardless of the value of t he pdr2 register and that of the ddr2 regist er, if the comparator analog input enable bit in the comparator control register ch. 0 (cmr0:vcid) is set to ?0?, the comparator input function is enabled. ? to disable the comparator input function, set the vcid bit to ?1?. ? for details of the comparator, refer to ?chapter 29 comparator? in ?new 8fx mb95710m/770m series hard- ware manual?. 19.4 port 6 port 6 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.4.1 port 6 configuration port 6 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 6 data register (pdr6) ? port 6 direction register (ddr6) 19.4.2 block diagrams of port 6 ? p60/seg06 pin this pin has the following peripheral function: ? lcdc seg06 output pin (seg06) ? p61/seg07 pin this pin has the following peripheral function: ? lcdc seg07 output pin (seg07) ? p62/seg08 pin this pin has the following peripheral function: ? lcdc seg08 output pin (seg08) ? p63/seg09 pin this pin has the following peripheral function: ? lcdc seg09 output pin (seg09)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 104 of 172 ? p64/seg10 pin this pin has the following peripheral function: ? lcdc seg10 output pin (seg10) ? p65/seg11 pin this pin has the following peripheral function: ? lcdc seg11 output pin (seg11) ? p66/seg12 pin this pin has the following peripheral function: ? lcdc seg12 output pin (seg12) ? p67/seg13 pin this pin has the following peripheral function: ? lcdc seg13 output pin (seg13) ? block diagram of p60/seg06, p61/ seg07, p62/seg08, p63/seg09, p6 4/seg10, p65/seg11, p66/seg12 and p67/seg13 19.4.3 port 6 registers ? port 6 register functions ? correspondence between registers and pins for port 6 register abbreviation data read read by read-modify-write (rmw) instruction write pdr6 0 pin state is ?l? level. pdr6 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr6 value is ?1?. as output port, outputs ?h? level. ddr6 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name p67 p66 p65 p64 p63 p62 p61 p60 pdr6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr6 pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write ddr6 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 105 of 172 19.4.4 port 6 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 6 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr6 register to external pins. ? if data is written to the pdr6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr6 register returns the pdr6 register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 3 (lcdce3:seg[0 7:06]) or in the lcdc enable register 4 (lcdce4:seg[13:0 8]) to ?0? to select the gen- eral-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lc- dce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddr6 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr6 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr6 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr6 register, th e pdr6 register va lue is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 3 (lcdce3:seg[0 7:06]) or in the lcdc enable register 4 (lcdce4:seg[13:0 8]) to ?0? to select the gen- eral-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as an lcdc segment output pin ? set the bit in the ddr6 register corresp onding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enable re gister 3 (lcdce3:seg[07:06]) or in the lcdc enable register 4 (lc- dce4:seg[13:08]) to ?1? to select the lcdc segment ou tput function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddr6 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr6 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 106 of 172 19.5 port 9 port 9 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.5.1 port 9 configuration port 9 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 9 data register (pdr9) ? port 9 direction register (ddr9) 19.5.2 block diagrams of port 9 ? p90/v4 pin this pin has the following peripheral function: ? lcd drive power supply pin (v4) ? p91/v3 pin this pin has the following peripheral function: ? lcd drive power supply pin (v3) ? p92/v2 pin this pin has the following peripheral function: ? lcd drive power supply pin (v2) ? p93/v1 pin this pin has the following peripheral function: ? lcd drive power supply pin (v1) ? block diagram of p90/v4, p91/v3, p92/v2 and p93/v1 pdr9 pin pdr9 read pdr9 write executing bit manipulation instruction ddr9 read ddr9 write ddr9 0 1 stop mode, watch mode (spl = 1) lcd power supply lcd power supply enable internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 107 of 172 19.5.3 port 9 registers ? port 9 register functions ? correspondence between registers and pins for port 9 19.5.4 port 9 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 9 register corresponding to that pin is set to ?1?. ? when a pin is used as an output port, it outputs the value of the pdr9 register to external pins. ? if data is written to the pdr9 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr9 register returns the pdr9 register value. ? to use a pin shared with the lcdc as an output port, set th e bit corresponding to that pin in the ve[4:1] bits in the lcdc enable register 1 (lcdce1) to ?0? to select the general-purpose i/o port function. ? operation as an input port ? a pin becomes an input port if the bit in the ddr9 register corresponding to that pin is set to ?0?. ? if data is written to the pdr9 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr9 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr9 register, th e pdr9 register va lue is returned. ? to use a pin shared with the lcdc as an input port, set the bit corresponding to that pin in the ve[4:1] bits in the lcdce1 register to ?0? to select the general-purpose i/o port function. ? operation at reset if the cpu is reset, all bits in the ddr9 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr9 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an lcd drive power supply pin ? set the bit in the ddr9 register corresponding to an lcd drive power supply pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcd drive power supply pin, set the bit corresponding to that pin in the ve[ 4:1] bits in the lcdce1 regi ster to ?1? to select the lcd drive power supply function. register abbreviation data read read by read-modify-write (rmw) instruction write pdr9 0 pin state is ?l? level. pdr9 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr9 value is ?1?. as output port, outputs ?h? level. ddr9 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name----p93p92p91p90 pdr9 ----bit3bit2bit1bit0 ddr9
mb95710m series mb95770m series document number: 002-09307 rev. *d page 108 of 172 19.6 port a port a is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.6.1 port a configuration port a is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port a data register (pdra) ? port a direction register (ddra) 19.6.2 block diagrams of port a ? pa0/com0 pin this pin has the following peripheral function: ? lcdc com0 output pin (com0) ? pa1/com1 pin this pin has the following peripheral function: ? lcdc com1 output pin (com1) ? pa2/com2 pin this pin has the following peripheral function: ? lcdc com2 output pin (com2) ? pa3/com3 pin this pin has the following peripheral function: ? lcdc com3 output pin (com3) ? pa4/com4 pin this pin has the following peripheral function: ? lcdc com4 output pin (com4) ? pa5/com5 pin this pin has the following peripheral function: ? lcdc com5 output pin (com5) ? pa6/com6 pin this pin has the following peripheral function: ? lcdc com6 output pin (com6) ? pa7/com7 pin this pin has the following peripheral function: ? lcdc com7 output pin (com7)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 109 of 172 ? block diagram of pa0/com0, pa1/com1, pa2/com2 , pa3/com3, pa4/com4, pa5/com5, pa6/com6 and pa7/com7 19.6.3 port a registers ? port a register functions ? correspondence between registers and pins for port a register abbreviation data read read by read-modify-write (rmw) instruction write pdra 0 pin state is ?l? level. pdra value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdra value is ?1?. as output port, outputs ?h? level. ddra 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pdra bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddra pdra pin pdra read pdra write executing bit manipulation instruction ddra read ddra write ddra 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 110 of 172 19.6.4 port a operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr a register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdra register to external pins. ? if data is written to the pdra register, the value is stored in the output latch and is outpu t to the pin set as an output port as it is. ? reading the pdra register returns the pdra register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 2 (lcdce2:com[7:0]) to ?0? to select the general-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lcdce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddra register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdra register, the value is stor ed in the output latch but is not output to the pin set as an input port. ? reading the pdra register returns the pin value. howeve r, if the read-modify-write (rmw) type of instruction is used to read the pdra register, the pdra register value is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 2 (lcdce2:com[7:0]) to ?0? to select the general-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as an lcdc common output pin ? set the bit in the ddra register corresponding to an lcdc common output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc common output pin, set a corresponding function select bit in the lcdc enable register 2 (lcdce2:com[7: 0]) to ?1? to select the l cdc common outp ut function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddra register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddra reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 111 of 172 19.7 port b port b is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.7.1 port b configuration port b is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port b data register (pdrb) ? port b direction register (ddrb) 19.7.2 block diagrams of port b ? pb0/seg00 pin this pin has the following peripheral function: ? lcdc seg00 output pin (seg00) ? pb1/seg01 pin this pin has the following peripheral function: ? lcdc seg01 output pin (seg01) ? block diagram of pb0 /seg00 and pb1/seg01 pdrb pin pdrb read pdrb write executing bit manipulation instruction ddrb read ddrb write ddrb 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 112 of 172 19.7.3 port b registers ? port b register functions ? correspondence between registers and pins for port b 19.7.4 port b operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr b register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrb register to external pins. ? if data is written to the pdrb register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrb register returns the pdrb register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 3 (lcdce3:seg[01:00]) to ?0? to select the general -purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lcdce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddrb register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrb register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrb register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdrb register, th e pdrb register value is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 3 (lcdce3:seg[01 :00]) to ?0? to select the general-purpose i/o port function, and th en set the pictl bit in the lcdce1 re gister to ?1?. ? operation as an lcdc segment output pin ? set the bit in the ddrb register correspo nding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enabl e register 3 (lcdce3:seg[01:00]) to ?1? to select the lcdc segment output function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddrb register are initialized to ?0? and port input is enabled. register abbreviation data read read by read-modify-write (rmw) instruction write pdrb 0 pin state is ?l? level. pdrb value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrb value is ?1?. as output port, outputs ?h? level. ddrb 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name------pb1pb0 pdrb ------bit1bit0 ddrb
mb95710m series mb95770m series document number: 002-09307 rev. *d page 113 of 172 ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to en ter the high impedance state regardless of the ddrb reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. 19.8 port c port c is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.8.1 port c configuration port c is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port c data register (pdrc) ? port c direction register (ddrc) 19.8.2 block diagrams of port c ?pc0/seg02 pin this pin has the following peripheral function: ? lcdc seg02 output pin (seg02) ?pc1/seg03 pin this pin has the following peripheral function: ? lcdc seg03 output pin (seg03) ?pc2/seg04 pin this pin has the following peripheral function: ? lcdc seg04 output pin (seg04) ?pc3/seg05 pin this pin has the following peripheral function: ? lcdc seg05 output pin (seg05)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 114 of 172 ? block diagram of pc0/seg02, pc 1/seg03, pc2/seg04 and pc3/seg05 19.8.3 port c registers ? port c register functions ? correspondence between registers and pins for port c register abbreviation data read read by read-modify-write (rmw) instruction write pdrc 0 pin state is ?l? level. pdrc value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrc value is ?1?. as output port, outputs ?h? level. ddrc 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name----pc3pc2pc1pc0 pdrc ----bit3bit2bit1bit0 ddrc pdrc pin pdrc read pdrc write executing bit manipulation instruction ddrc read ddrc write ddrc 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 115 of 172 19.8.4 port c operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr c register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrc register to external pins. ? if data is written to the pdrc register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrc register returns the pdrc register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 3 (lcdce3:seg[05:02]) to ?0? to select the general -purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lcdce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddrc register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrc register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrc register returns the pin value. however, if the read-modif y-write (rmw) type of instruction is used to read the pdrc register, th e pdrc register value is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 3 (lcdce3:seg[05 :02]) to ?0? to select the general-purpose i/o port function, and th en set the pictl bit in the lcdce1 re gister to ?1?. ? operation as an lcdc segment output pin ? set the bit in the ddrc register correspondi ng to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enabl e register 3 (lcdce3:seg[05:02]) to ?1? to select the lcdc segment output function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddrc register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to en ter the high impedance state regardless of the ddrc reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 116 of 172 19.9 port e port e is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.9.1 port e configuration port e is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port e data register (pdre) ? port e direction register (ddre) 19.9.2 block diagrams of port e ? pe0/seg14 pin this pin has the following peripheral function: ? lcdc seg14 output pin (seg14) ? pe1/seg15 pin this pin has the following peripheral function: ? lcdc seg15 output pin (seg15) ? pe2/seg16 pin this pin has the following peripheral function: ? lcdc seg16 output pin (seg16) ? pe3/seg17 pin this pin has the following peripheral function: ? lcdc seg17 output pin (seg17) ? pe4/seg18 pin this pin has the following peripheral function: ? lcdc seg18 output pin (seg18) ? block diagram of pe0/seg 14, pe1/seg15, pe2/seg16, pe3/seg17 and pe4/seg18 pdre pin pdre read pdre write executing bit manipulation instruction ddre read ddre write ddre 0 1 stop mode, watch mode (spl = 1) lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 117 of 172 ? pe5/seg19/to11 pin this pin has the following peripheral functions: ? lcdc seg19 output pin (seg19) ? 8/16-bit composite timer ch. 1 output pin (to11) ? pe6/seg20/to10 pin this pin has the following peripheral functions: ? lcdc seg20 output pin (seg20) ? 8/16-bit composite timer ch. 1 output pin (to10) ? pe7/seg21/ec1 pin this pin has the following peripheral functions: ? lcdc seg21 output pin (seg21) ? 8/16-bit composite timer ch. 1 clock input pin (ec1) ? block diagram of pe5/seg19/to11, pe6/seg20/to10 and pe7/seg21/ec1 19.9.3 port e registers ? port e register functions ? correspondence between registers and pins for port e register abbreviation data read read by read-modify-write (rmw) instruction write pdre 0 pin state is ?l? level. pdre value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdre value is ?1?. as output port, outputs ?h? level. ddre 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pdre bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddre pdre pin pdre read pdre write executing bit manipulation instruction ddre read ddre write ddre 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output lcd output internal bus lcd output enable
mb95710m series mb95770m series document number: 002-09307 rev. *d page 118 of 172 19.9.4 port e operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr e register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdre register to external pins. ? if data is written to the pdre register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdre register returns the pdre register value. ? to use a pin shared with the lcdc as an output port, set a corresponding function select bit in the lcdc enable register 4 (lcdce4:seg[1 5:14]) or in the lcdc enable register 5 (lcdce5:seg[21:1 6]) to ?0? to select the gen- eral-purpose i/o port function, and then set the port input control bit in the lcdc enable register 1 (lc- dce1:pictl) to ?1?. ? operation as an input port ? a pin becomes an input port if the bit in the ddre register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdre register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdre register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdre register, th e pdre register value is returned. ? to use a pin shared with the lcdc as an input port, set a corresponding func tion select bit in the lcdc enable register 4 (lcdce4:seg[1 5:14]) or in the lcdc enable register 5 (lcdce5:seg[21:1 6]) to ?0? to select the gen- eral-purpose i/o port function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdre register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdre register. however, if the read- modify-write (rmw) type of instruction is used to read the pdre register, the pdre register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddre regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdre register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. however, if the re ad-modify-write (rmw) type of instruction is used to read the pdre register, the pdre register value is returned. ? operation as an lcdc segment output pin ? set the bit in the ddre register correspo nding to an lcdc segment output pin to ?0?. ? to use a pin shared with a general-purpose i/o port as an lcdc segment output pin, set a corresponding function select bit in the lcdc enable re gister 4 (lcdce4:seg[15:14]) or in the lcdc enable register 5 (lc- dce5:seg[21:16]) to ?1? to select the lcdc segment ou tput function, and then set the pictl bit in the lcdce1 register to ?1?. ? operation at reset if the cpu is reset, all bits in the ddre register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to en ter the high impedance state regardless of the ddre reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 119 of 172 ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. 19.10 port f port f is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.10.1 port f configuration port f is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port f data register (pdrf) ? port f direction register (ddrf) 19.10.2 block diagrams of port f ?pf0/x0 pin this pin has the following peripheral function: ? main clock input oscillation pin (x0) ?pf1/x1 pin this pin has the following peripheral function: ? main clock i/o oscillation pin (x1) ? block diagram of pf0/x0 and pf1/x1 pdrf pin pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 stop mode, watch mode (spl = 1) internal bus hysteresis
mb95710m series mb95770m series document number: 002-09307 rev. *d page 120 of 172 ?pf2/rst pin this pin has the following peripheral function: ? reset pin (rst ) ? block diagram of pf2/rst 19.10.3 port f registers ? port f register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port f *: pf2/rst is the dedicated reset pin on mb95f774m/f776m/f778m. register abbreviation data read read by read-modify-write (rmw) instruction write pdrf 0 pin state is ?l? level. pdrf value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrf value is ?1?. as output port, outputs ?h? level.* ddrf 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name-----pf2 * pf1 pf0 pdrf -----bit2bit1bit0 ddrf pdrf pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 1 0 stop mode, watch mode (spl = 1) reset input reset input enable reset output enable reset output pin od internal bus hysteresis
mb95710m series mb95770m series document number: 002-09307 rev. *d page 121 of 172 19.10.4 port f operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr f register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrf register to external pins. ? if data is written to the pdrf register, the value is stored in the output latch and is outpu t to the pin set as an output port as it is. ? reading the pdrf register returns the pdrf register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddrf register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrf register , the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrf register returns the pin value. howeve r, if the read-modify-write (rmw) type of instruction is used to read the pdrf register, t he pdrf register value is returned. ? operation at reset if the cpu is reset, all bits in the ddrf register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddrf reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. 19.11 port g port g is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapters in ?new 8fx mb95710m/770m series hardware manual?. 19.11.1 port g configuration port g is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port g data register (pdrg) ? port g direction register (ddrg) ? port g pull-up register (pulg) 19.11.2 block diagram of port g ? pg1/x0a pin this pin has the following peripheral function: ? subclock input oscillation pin (x0a) ? pg2/x1a pin this pin has the following peripheral function: ? subclock i/o oscillation pin (x1a)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 122 of 172 ? block diagram of pg1/x0a and pg2/x1a 19.11.3 port g registers ? port g register functions ? correspondence between registers and pins for port g register abbreviation data read read by read-modify-write (rmw) instruction write pdrg 0 pin state is ?l? level. pdrg value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrg value is ?1?. as output port, outputs ?h? level. ddrg 0 port input enabled 1 port output enabled pulg 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name-----pg2pg1- pdrg -----bit2bit1- ddrg pulg pdrg pin pdrg read pdrg write executing bit manipulation instruction ddrg read ddrg write pulg read pulg write ddrg pulg 0 1 stop mode, watch mode (spl = 1) hysteresis pull-up internal bus
mb95710m series mb95770m series document number: 002-09307 rev. *d page 123 of 172 19.11.4 port g operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr g register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrg regi ster to external pins. ? if data is written to the pdrg register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrg register returns the pdrg register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddrg register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrg register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrg register returns the pin value. however, if the read-modify-write (rmw) type of instruction is used to read the pdrg register, th e pdrg register va lue is returned. ? operation at reset if the cpu is reset, all bits in the ddrg register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is comp ulsorily made to enter th e high impedance state regardless of the ddrg reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pulg register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pulg register.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 124 of 172 20. interrupt source table interrupt source interrupt request number vector table address interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower register bit external interrupt ch. 0 irq00 0xfffa 0xfffb ilr0 l00 [1:0] high low external interrupt ch. 4 external interrupt ch. 1 irq01 0xfff8 0xfff9 ilr0 l01 [1:0] external interrupt ch. 5 external interrupt ch. 2 irq02 0xfff6 0xfff7 ilr0 l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 0xfff4 0xfff5 ilr0 l03 [1:0] external interrupt ch. 7 uart/sio ch. 0 irq04 0xfff2 0xfff3 ilr1 l04 [1:0] low-voltage detection circuit 8/16-bit composite timer ch. 0 (lower) irq05 0xfff0 0xfff1 ilr1 l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 0xffee 0xffef ilr1 l06 [1:0] uart/sio ch. 2 irq07 0xffec 0xffed ilr1 l07 [1:0] lcdc irq08 0xffea 0xffeb ilr2 l08 [1:0] 8/16-bit ppg ch. 1 (lower) irq09 0xffe8 0xffe9 ilr2 l09 [1:0] uart/sio ch. 1 8/16-bit ppg ch. 1 (upper) irq10 0xffe6 0xffe7 ilr2 l10 [1:0] 16-bit reload timer ch. 0 irq11 0xffe4 0xffe5 ilr2 l11 [1:0] 8/16-bit ppg ch. 0 (upper) irq12 0xffe2 0xffe3 ilr3 l12 [1:0] 8/16-bit ppg ch. 0 (lower) irq13 0xffe0 0xffe1 ilr3 l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 0xffde 0xffdf ilr3 l14 [1:0] comparator ch. 0 irq15 0xffdc 0xffdd ilr3 l15 [1:0] i 2 c bus interface ch. 0 irq16 0xffda 0xffdb ilr4 l16 [1:0] ? irq17 0xffd8 0xffd9 ilr4 l17 [1:0] 8/12-bit a/d converter irq18 0xffd6 0xffd7 ilr4 l18 [1:0] time-base timer irq19 0xffd4 0xffd5 ilr4 l19 [1:0] watch prescaler irq20 0xffd2 0xffd3 ilr5 l20 [1:0] watch counter ? irq21 0xffd0 0xffd1 ilr5 l21 [1:0] 8/16-bit composite timer ch. 1 (lower) irq22 0xffce 0xffcf ilr5 l22 [1:0] flash memory irq23 0xffcc 0xffcd ilr5 l23 [1:0]
mb95710m series mb95770m series document number: 002-09307 rev. *d page 125 of 172 21. pin states in each mode pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 pf0/x0 oscillation input oscillatio n input hi-z hi-z hi-z hi-z oscillation input* 1 i/o port* 2 i/o port* 2 - previous state kept - input blocked* 2, * 3 -hi-z - input blocked* 2, * 3 - previous state kept - input blocked* 2, * 3 -hi-z - input blocked* 2, * 3 -hi-z - input enabled* 4 (however, it does not function.) pf1/x1 oscillation input oscillatio n input hi-z hi-z hi-z hi-z oscillation input* 1 i/o port* 2 i/o port* 2 - previous state kept - input blocked* 2, * 3 -hi-z - input blocked* 2, * 3 - previous state kept - input blocked* 2, * 3 -hi-z - input blocked* 2, * 3 -hi-z - input enabled* 4 (however, it does not function.) pf2/rst reset input reset input reset input reset input reset input reset input reset input* 5 i/o port* 2 i/o port* 2 - previous state kept - input blocked* 2, * 3 -hi-z - input blocked* 2, * 3 - previous state kept - input blocked* 2, * 3 -hi-z - input blocked* 2, * 3 -hi-z - input enabled* 4 (however, it does not function.) pg1/x0a oscillation input oscillatio n input hi-z hi-z hi-z hi-z oscillation input* 6 i/o port* 2 i/o port* 2 - previous state kept - input blocked* 2, * 3 -hi-z* 7 - input blocked* 2, * 3 - previous state kept - input blocked* 2, * 3 -hi-z* 7 - input blocked* 2, * 3 -hi-z - input enabled* 4 (however, it does not function.) pg2/x1a oscillation input oscillatio n input hi-z hi-z hi-z hi-z oscillation input* 6 i/o port* 2 i/o port* 2 - previous state kept - input blocked* 2, * 3 -hi-z* 7 - input blocked* 2, * 3 - previous state kept - input blocked* 2, * 3 -hi-z* 7 - input blocked* 2, * 3 -hi-z - input enabled* 4 (however, it does not function.) p00/int00/ an00/ seg29* 8 / uo2 i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 3 , * 10 -hi-z - input blocked* 3 , * 10 - previous state kept - input blocked* 3 , * 10 -hi-z - input blocked* 3 , * 10 -hi-z - input blocked* 3 p01/int01/ an01/ seg28* 8 / seg36* 8 / to00* 9 /ui2 p02/int02/ an02/ seg27* 8 / seg35* 8 / uck2 p03/int03/ an03/ seg26* 8 / seg34* 8 / uo1
mb95710m series mb95770m series document number: 002-09307 rev. *d page 126 of 172 pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 p04/int04/ an04/ seg25* 8 / seg33* 8 / ui1 i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 3 , * 10 -hi-z - input blocked* 3 , * 10 - previous state kept - input blocked* 3 , * 10 -hi-z - input blocked* 3 , * 10 -hi-z - input blocked* 3 p05/int05/ an05/ seg24* 8 / seg32* 8 / uck1 p06/int06/ an06/ seg23* 8 / seg31* 8 p07/int07/ an07/ seg22* 8 / seg30* 8 p10/ui0/ to0* 9 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z* 7 - input blocked* 3 - previous state kept - input blocked* 3 -hi-z* 7 - input blocked* 3 -hi-z - input enabled* 4 (however, it does not function.) p11/uo0 p12/dbg i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 ?h? - previous state kept - input blocked* 3 ?h? ?h? p13/adtg/ to01* 9 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z* 7 - input blocked* 3 - previous state kept - input blocked* 3 -hi-z* 7 - input blocked* 3 -hi-z - input enabled* 4 (however, it does not function.) p14/uck0/ ec0* 9 /ti0* 9 p15/ seg31* 8 / ppg11 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z - input blocked* 3 - previous state kept - input blocked* 3 -hi-z - input blocked* 3 -hi-z - input blocked* 3 p16/ seg30* 8 / ppg10 p17/ cmp0_o i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept* 11 - input blocked* 3 -hi-z* 7 - input blocked* 3 - previous state kept* 11 - input blocked* 3 -hi-z* 7 - input blocked* 3 -hi-z - input enabled* 4 (however, it does not function.) p20/ ppg00/ cmp0_n i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 3, * 12 -hi-z* 7 - input blocked* 3, * 12 - previous state kept - input blocked* 3, * 12 -hi-z* 7 - input blocked* 3, * 12 -hi-z - input enabled* 4 p21/ ppg01/ cmp0_p p22/scl i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3, * 13 -hi-z - input blocked* 3, * 13 - previous state kept - input blocked* 3, * 13 -hi-z - input blocked* 3, * 13 -hi-z - input enabled* 4 p23/sda
mb95710m series mb95770m series document number: 002-09307 rev. *d page 127 of 172 pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 p40/ seg21* 14 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z - input blocked* 3 - previous state kept - input blocked* 3 -hi-z - input blocked* 3 -hi-z - input blocked* 3 p41/ seg20* 14 p42/ seg19* 14 p43/ seg18* 14 p50/ to01* 14 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z* 7 - input blocked* 3 - previous state kept - input blocked* 3 -hi-z* 7 - input blocked* 3 -hi-z - input enabled* 4 (however, it does not function.) p51/ec0* 14 p52/ti0/ to00* 14 p53/to0* 14 p60/ seg06* 8 / seg10* 8 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z - input blocked* 3 - previous state kept - input blocked* 3 -hi-z - input blocked* 3 -hi-z - input blocked* 3 p61/ seg07* 8 / seg11* 8 p62/ seg08* 8 / seg12* 8 p63/ seg09* 8 / seg13* 8 p64/ seg10* 8 / seg14* 8 p65/ seg11* 8 / seg15* 8 p66/ seg12* 8 / seg16* 8 p67/ seg13* 8 / seg17* 8 p90/v4 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z - input blocked* 3 - previous state kept - input blocked* 3 -hi-z - input blocked* 3 -hi-z - input blocked* 3 p91/v3 p92/v2 p93/v1 p94/v0* 14
mb95710m series mb95770m series document number: 002-09307 rev. *d page 128 of 172 pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 pa0/com0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z - input blocked* 3 - previous state kept - input blocked* 3 -hi-z - input blocked* 3 -hi-z - input blocked* 3 pa1/com1 pa2/com2 pa3/com3 pa4/com4 pa5/com5 pa6/com6 pa7/com7 pb0/seg00 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z - input blocked* 3 - previous state kept - input blocked* 3 -hi-z - input blocked* 3 -hi-z - input blocked* 3 pb1/seg01 pb2/ seg37* 14 pb3/ seg38* 14 pb4/ seg39* 14 pc0/ seg02 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z - input blocked* 3 - previous state kept - input blocked* 3 -hi-z - input blocked* 3 -hi-z - input blocked* 3 pc1/ seg03 pc2/ seg04 pc3/ seg05 pc4/ seg06* 14 pc5/ seg07* 14 pc6/ seg08* 14 pc7/ seg09* 14
mb95710m series mb95770m series document number: 002-09307 rev. *d page 129 of 172 spl: pin state setting bit in the standby control register (stbc:spl) hi-z: high impedance *1: pf0/x0 and pf1/x1 transit to this state on a reset when configured as a main clock oscillation pins. *2: the pin stays at the state shown when configured as a general-purpose i/o port. *3: ?input blocked? means direct input gat e operation from the pin is disabled. *4: ?input enabled? means that the input function is enabled. while the input function is enabled, execute a pull-up op- eration or a pull-down operation to prevent leaks due to extern al input. if a pin is used as an output port, its pin state is the same as that of other ports. *5: the pf2/rst pin stays at the state shown when configured as a reset pin. *6: pg1/x0a and pg2/x1a transit to this state on a reset when config ured as subclock oscillation pins. *7: the pull-up control setting is still effective. *8: the mb95710m series and the mb95770m series have different seg output assignment as shown below. pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 pe0/ seg14* 8 / seg22* 8 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 3 -hi-z - input blocked* 3 - previous state kept - input blocked* 3 -hi-z - input blocked* 3 -hi-z - input blocked* 3 pe1/ seg15* 8 / seg23* 8 pe2/ seg16* 8 / seg24* 8 pe3/ seg17* 8 / seg25* 8 pe4/ seg18* 8 / seg26* 8 pe5/ seg19* 8 / seg27* 8 / to11 pe6/ seg20* 8 / seg28* 8 / to10 pe7/ seg21* 8 / seg29* 8 / ec1 seg output pin on mb95710m series pin on mb95770m series seg06 pc4 p60 seg07 pc5 p61 seg08 pc6 p62 seg09 pc7 p63 seg10 p60 p64 seg11 p61 p65 seg12 p62 p66 seg13 p63 p67 seg14 p64 pe0 seg15 p65 pe1 seg16 p66 pe2
mb95710m series mb95770m series document number: 002-09307 rev. *d page 130 of 172 *9: on the mb95770m series, to00 is assigned to p01, to0 to p10, to01 to p13, and ec0 and ti0 to p14. *10: though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *11: the output function of the comparator is still in operation in st op mode and watch mode. *12: though input is blocked, an analog signal can also be input to generate a comparator interrupt when the comparator interrupt is enabled. *13: the i 2 c bus interface can wake up the mcu in stop mo de or watch mode when its mcu standby mode wakeup function is enabled. for details of the mcu standby mode wakeup function, refer to ?chapter 23 i 2 c bus inter- face? in ?new 8fx mb95710m/770m series hardware manual?. *14: p40/seg21, p41/seg20, p42/seg19 , p43/seg18, p50/to01, p51/ec0, p52/ti0/to00, p53/to0, p94/v0, pb2/seg37, pb3/seg38, pb4/seg39, pc4/seg06, pc5/seg07, pc6/seg08 and pc7/seg09 are only avail- able on the mb95710m series. seg17 p67 pe3 seg18 p43 pe4 seg19 p42 pe5 seg20 p41 pe6 seg21 p40 pe7 seg22 pe0 p07 seg23 pe1 p06 seg24 pe2 p05 seg25 pe3 p04 seg26 pe4 p03 seg27 pe5 p02 seg28 pe6 p01 seg29 pe7 p00 seg30 p07 p16 seg31 p06 p15 seg32 p05 ? seg33 p04 ? seg34 p03 ? seg35 p02 ? seg36 p01 ? seg output pin on mb95710m series pin on mb95770m series
mb95710m series mb95770m series document number: 002-09307 rev. *d page 131 of 172 22. electrical characteristics 22.1 absolute maximum ratings *1: these parameters are based on the condition that v ss is 0.0 v. *2: v 1 and v 0 must not exceed v cc + 0.3 v. v 1 must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. *3: specific pins: p00 to p07, p10, p11, p13 to p16, p20 to p22, p40 to p43, p5 0 to p53, p60 to p67, p90 to p94, pa0 to pa7, pb0 to pb4, pc0 to pc7, pe0 to pe7, pf0, pf1, pg1, pg2 (p40 to p4 3, p50 to p53, p94, pb2 to pb4 and pc4 to pc7 are only available on the mb95710m series.) ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontro ller before applying the hv (high voltage) signal. parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6v input voltage* 1 v i v ss ? 0.3 v ss + 6v*2 output voltage* 1 v o v ss ? 0.3 v ss + 6v*2 maximum clamp current i clamp ? 2 + 2 ma applicable to specific pins* 3 total maximum clamp current |i clamp | ? 20 ma applicable to specific pins* 3 ?l? level maximum output current i ol ?15ma ?l? level average current i olav ?4ma average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ?50ma total average output current = operating current operating ratio (total number of pins) ?h? level maximum output current i oh ? ? 15 ma ?h? level average current i ohav ? ? 4ma average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total number of pins) power consumption p d ? 320 mw operating temperature t a ? 40 + 85 c storage temperature t stg ? 55 + 150 c
mb95710m series mb95770m series document number: 002-09307 rev. *d page 132 of 172 ? the value of the limiting resistor should be set to a valu e at which the current to be input to the microcontroller pin when the hv (high voltage) signal is in put is below the standard value, irrespecti ve of whether the current is transient current or stationary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcon troller power supply is off (not fixed at 0 v), since power is supplied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, si nce power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: warning: semiconductor devices may be permanently da maged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolu te maximum ratings. do not exceed any of these ratings. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor ? input/output equivalent circuit
mb95710m series mb95770m series document number: 002-09307 rev. *d page 133 of 172 22.2 recommended operating conditions (v ss = 0.0 v) *1: the minimum power supply voltage becomes 2.18 v when a product with the low-voltage detection reset is used or when the on-chip debug mode is used. *2: use a ceramic capacitor or a capacitor with equivalent fr equency characteristics. for th e connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distan ce between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be und er their recommended op erating condition. operation under any conditio ns other than these conditions may adve rsely affect reliab ility of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 1.8* 1 5.5 v in normal operation decoupling capacitor c s 0.2 10 f a capacitor of about 1.0 f is recommended. * 2 operating temperature t a ? 40 + 85 c other than on-chip debug mode + 5 + 35 on-chip debug mode c cs dbg * rst ? dbg / rst / c pins connection diagram *: connect the dbg pin to an exte rnal pull-up resistor of 2 k or above. after power-on, ensure that the dbg pin does not stay at ?l? level until the rese t output is released. the dbg pin becomes a com- munication pin in debug mode. since the actual pull- up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
mb95710m series mb95770m series document number: 002-09307 rev. *d page 134 of 172 22.3 dc characteristics (v cc = 3.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ihi p01, p04, p10, p22, p23 *1 0.7 v cc ?v cc + 0.3 v v ihs p00 to p07, p10 to p17, p20 to p23, p40 to p43* 2 , p50 to p53* 2 , p60 to p67, p90 to p93, p94* 2 , pa0 to pa7, pb0, pb1, pb2 to pb4* 2 , pc0 to pc3, pc4 to pc7* 2 , pe0 to pe7, pf0, pf1, pg1, pg2 *1 0.8 v cc ?v cc + 0.3 v hysteresis input v ihm pf2 ? 0.7 v cc ?v cc + 0.3 v hysteresis input ?l? level input voltage v ili p01, p04, p10, p22, p23 *1 v ss ? 0.3 ? 0.3 v cc v v ils p00 to p07, p10 to p17, p20 to p23, p40 to p43* 2 , p50 to p53* 2 , p60 to p67, p90 to p93, p94* 2 , pa0 to pa7, pb0, pb1, pb2 to pb4* 2 , pc0 to pc3, pc4 to pc7* 2 , pe0 to pe7, pf0, pf1, pg1, pg2 *1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ? 0.3 ? 0.3 v cc v hysteresis input open-drain output application voltage v d p12, p22, p23, pf2 ?v ss ? 0.3 ? v ss + 5.5 v ?h? level output voltage v oh output pins other than p12, p22, p23, pf2 i oh = ? 4 ma* 3 v cc ? 0.5 ? ? v
mb95710m series mb95770m series document number: 002-09307 rev. *d page 135 of 172 (v cc = 3.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max ?l? level output voltage v ol all output pins i ol = 4 ma* 4 ??0.4v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc ? 5? + 5a when the internal pull-up resistor is disabled internal pull-up resistor r pull p10, p11, p13, p14, p17, p20, p21, p50 to p53* 2 , pg1, pg2 v i = 0 v 75 100 150 k when the internal pull-up resistor is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf
mb95710m series mb95770m series document number: 002-09307 rev. *d page 136 of 172 (v cc = 3.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ* 1 max* 5 power supply current* 6 i cc v cc (external clock operation) f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?4.77.3ma except during flash memory programming and erasing ?9.815.8ma during flash memory programming and erasing i ccs f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?2.13.4ma i ccl f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = + 25 c ?3560a i ccls f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = + 25 c ?2 7a i cct f cl = 32 khz watch mode main stop mode t a = + 25 c ?1.26.2 a i ccmpll v cc f mpll = 16 mhz f mp = 16 mhz main pll clock mode (multiplied by 4) ?5.38.5ma i ccmcrpll f mcrpll = 16 mhz f mp = 16 mhz main cr pll clock mode (multiplied by 4) ?4.98.3ma i ccmcr f crh = 4 mhz f mp = 4 mhz main cr clock mode ?1.73.4ma i ccscr sub-cr clock mode t a = + 25 c ?54100a
mb95710m series mb95770m series document number: 002-09307 rev. *d page 137 of 172 (v cc = 3.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ* 1 max* 5 power supply current* 6 i ccts v cc (external clock operation) f ch = 32 mhz time-base timer mode t a = + 25 c ?450500a i cch substop mode t a = + 25 c ?0.7 5 a i a av cc f ch = 16 mhz current consumption of the a/d converter ?1.83.2ma i ah f ch = 16 mhz current consumption with the a/d converter halted ?0.11.7a i v f ch = 16 mhz current consumption of the comparator ?160700a i plvd v cc current consumption of the low-voltage detection reset circuit in operation ?626a i ilvd current consumption of the low-voltage detection interrupt circuit operating in normal mode ?614a i ilvdl current consumption of the low-voltage detection interrupt circuit operating in low power consumption mode ?310a i crh current consumption of the main cr oscillator ?270320a i crl current consumption of the sub-cr oscillator oscillating at 100 khz ?520a i sosc current consumption of the suboscillator ?0.8 7 a
mb95710m series mb95770m series document number: 002-09307 rev. *d page 138 of 172 (v cc = 3.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: v cc = 3.0 v, t a = + 25 c *2: p40 to p43, p50 to p53, p94, pb2 to pb4 are only available on the mb95710m series. *3: when v cc is smaller than 4.5 v, the condition becomes i oh = ? 2 ma. *4: when v cc is smaller than 4.5 v, the condition becomes i ol = 2 ma. *5: v cc = 3.3 v, t a = + 85 c (unless otherwise specified) *6: ? the power supply current is determined by the external clock. when the low-voltage detection reset circuit is se- lected, the power supply current is the sum of adding th e current consumption of the low-voltage detection reset circuit (i plvd ) to one of the values from i cc to i cch . in addition, when both the low-voltage detection reset circuit and a cr oscillator are selected, the power su pply current is the sum of adding up the current consumption of the low- voltage detection reset circuit (i plvd ), the current c onsumption of the cr oscillator (i crh or i crl ) and one of the val- ues from i cc to i cch . in on-chip debug mode, the main cr oscillator (i crh ) and the low-voltage detection reset circuit are always in operation, and current consumption therefore increases accordingly. ? see ?4. ac characteristics clock timing? for f ch , f cl , f crh , f mcrpll and f mpll . ? see ?4. ac characteristics so urce clock/machin e clock? for f mp and f mpl . ? the power supply current in subclock mode is determin ed by the external clock. in subclock mode, current con- sumption in using the crystal oscillator is higher than that in using the external clock. when the crystal oscillator is used, the power supply current is the sum of adding i sosc (current consumption of th e suboscillator) to the power supply current in using the external cl ock. for details of controlling the subclock, refer to ?chapter 3 clock controller? and ?chapter 30 sy stem configuration register? in ?new 8fx mb95710m/770m se- ries hardware manual?. *7: seg32 to seg39 are only available on the mb95710m series. *8: v0 is only available on the mb95710m series. parameter symbol pin name condition value unit remarks min typ* 1 max* 5 lcd internal division resistance r lcd ? between v4 and v ss ?400?k ?40?k com0 to com7 output impedance r vcom com0 to com7 v1 to v4 = 4.1 v ?? 5k seg00 to seg39* 7 output impedance r vseg seg00 to seg39* 7 ?? 7k lcd leakage current i lcdl v0* 8 to v4, com0 to com7, seg00 to seg39* 7 ? ? 1? + 1a
mb95710m series mb95770m series document number: 002-09307 rev. *d page 139 of 172 22.4 ac characteristics 22.4.1 clock timing (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 ? 1 ? 32.5 mhz when the main external clock is used x0, x1 ? 4 ? 8.13 mhz operating conditions ? the main clock is used. ? pll multiplication rate: 2 4?6.5mhz operating conditions ? the main clock is used. ? pll multiplicat ion rate: 2.5 4 ? 5.41 mhz operating conditions ? the main clock is used. ? pll multiplication rate: 3 4 ? 4.06 mhz operating conditions ? the main clock is used. ? pll multiplication rate: 4 f crh ?? 3.92 4 4.08 mhz operating conditions ? the main cr clock is used. ?0 c t a + 70 c 3.8 4 4.2 mhz operating conditions ? the main cr clock is used. ? ? 40 c t a < 0 c, + 70 c < t a + 85 c f mcrpll ?? 7.84 8 8.16 mhz operating conditions ? pll multiplication rate: 2 ?0 c t a + 70 c 7.6 8 8.4 mhz operating conditions ? pll multiplication rate: 2 ? ? 40 c t a < 0 c, + 70 c < t a + 85 c 9.8 10 10.2 mhz operating conditions ? pll multiplicat ion rate: 2.5 ?0 c t a + 70 c 9.5 10 10.5 mhz operating conditions ? pll multiplicat ion rate: 2.5 ? ? 40 c t a < 0 c, + 70 c < t a + 85 c 11.76 12 12.24 mhz operating conditions ? pll multiplication rate: 3 ?0 c t a + 70 c 11.4 12 12.6 mhz operating conditions ? pll multiplication rate: 3 ? ? 40 c t a < 0 c, + 70 c < t a + 85 c
mb95710m series mb95770m series document number: 002-09307 rev. *d page 140 of 172 (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max clock frequency f mcrpll ?? 15.68 16 16.32 mhz operating conditions ? pll multiplication rate: 4 ?0 c t a + 70 c 15.2 16 16.8 mhz operating conditions ? pll multiplication rate: 4 ? ? 40 c t a < 0 c, + 70 c < t a + 85 c f mpll ??8?16mhz when the main pll clock is used f cl x0a, x1a ?? ? 32.768 ? khz when the sub-oscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 150 khz when the sub-cr clock is used clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 ? 30.8 ? 1000 ns when an external clock is used x0, x1 ? ? 250 ? ns when the main pll clock is used t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used input clock pulse width t wh1 , t wl1 x0 ? 12.4 ? ? ns when an external clock is used, the duty ratio should range between 40% and 60%. x0, x1 ? ? 125 ? ns when the main pll clock is used t wh2 , t wl2 x0a ? ? 15.2 ? s when an external clock is used, the duty ratio should range between 40% and 60%. input clock rising time and falling time t cr , t cf x0, x0a ? ? ? 5 ns when an external clock is used cr oscillation start time t crhwk ????50s when the main cr clock is used t crlwk ????30s when the sub-cr clock is used pll oscillation start time t mcrpllwk ????100s when the main cr pll clock is used
mb95710m series mb95770m series document number: 002-09307 rev. *d page 141 of 172 x0, x1 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf ? input waveform generated when an external clock (main clock) is used x0 x1 f ch x0 f ch when an external clock is used when a crystal oscillator or a ceramic oscillator is used ? figure of main clock inpu t port external connection x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf ? input waveform generated when an external clock (subclock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0a x1a x0a f cl f cl ? figure of subclock input port external connection
mb95710m series mb95770m series document number: 002-09307 rev. *d page 142 of 172 t crhwk 1/f crh main cr clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (main cr clock) is used t crlwk 1/f crl sub-cr clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (sub-cr clock) is used t mcrpllwk 1/f mcrpll main cr pll clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (main cr pll clock) is used
mb95710m series mb95770m series document number: 002-09307 rev. *d page 143 of 172 22.4.2 source clock/machine clock (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 ? 250 ? ns when the main cr clock is used 62.5 ? 250 ns when the main pll clock is used min: f ch = 4 mhz, multiplied by 4 max: f ch = 4 mhz, no division 62.5 ? 250 ns when the main cr pll clock is used min: f crh = 4 mhz, multiplied by 4 max: f crh = 4 mhz, no division ?61?s when the sub-oscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f cl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used ? 4 ? mhz when the main cr clock is used 8 ? 16 mhz when the main pll clock is used 8 ? 16 mhz when the main cr pll clock is used f spl ? 16.384 ? khz when t he sub-oscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 250 ? 4000 ns when the main cr clock is used min: f sp = 4 mhz, no division max: f sp = 4 mhz, divided by 16 62.5 ? 2000 ns when the main pll clock is used min: f sp = 4 mhz, multiplied by 4 max: f sp = 4 mhz, divided by 16 62.5 ? 2000 ns when the main cr pll clock is used min: f sp = 4 mhz, multiplied by 4 max: f sp = 4 mhz, divided by 16 61 ? 976.5 s when the sub-oscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16
mb95710m series mb95770m series document number: 002-09307 rev. *d page 144 of 172 (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: this is the clock before it is divided according to the di vision ratio set by the machine cl ock division ratio select bits (sycc:div[1:0]). this source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (sycc:div[1:0]). in addit ion, a source clock can be selected from the follow- ing. ? main clock divided by 2 ? pll multiplication of main clock (select a multiplication rate from 2, 2.5, 3 and 4.) ? main cr clock ? pll multiplication of main cr clock (select a multiplication rate from 2, 2.5, 3 and 4.) ? subclock divided by 2 ? sub-cr clock divided by 2 *2: this is the operating clock of the microcontrolle r. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.25 ? 4 mhz when the main cr clock is used 0.5 ? 16 mhz when the main pll clock is used 0.5 ? 16 mhz when the main cr pll clock is used f mpl 1.024 ? 16.384 khz when the sub- oscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
mb95710m series mb95770m series document number: 002-09307 rev. *d page 145 of 172 f ch (main oscillation clock) divided by 2 divided by 2 divided by 2 f crh (main cr clock) f mcrpll (main cr pll clock) f cl (suboscillation clock) f crl (sub-cr clock) f mpll (main pll clock) sclk (source clock) mclk (machine clock) machine clock divide ratio select bits (sycc:div[1:0]) clock mode select bits (sycc:scs[2:0]) division circuit 1 1/4 1/8 1/16 ? schematic diagram of the clock generation block operating voltage (v) a/d converter operation range 5.5 3 mhz 16 khz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.8 1.5 0.0 ? 40 c to + 85 c)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 146 of 172 22.4.3 external reset (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *: see ?source clock/machine clock? for t mclk . 22.4.4 power-on reset (v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk *?ns parameter symbol pin name value unit remarks min typ max power supply rising time dv/dt v cc 0.1 ? ? v/ms power supply cutoff time t off 1??ms reset release voltage v deth 1.44 1.60 1.76 v at voltage rise reset detection voltage v detl 1.39 1.55 1.71 v at voltage fall reset release delay time t ond ? ? 10 ms dv/dt 0.1 mv/s reset detection delay time t offd ??0.4msdv/dt ? 0.04 mv/s 0.2 v cc rst 0.2 v cc t rstl v deth v cc power-on reset v detl 0.2 v t off t offd t ond dv dt 0.2 v
mb95710m series mb95770m series document number: 002-09307 rev. *d page 147 of 172 22.4.5 peripheral input timing (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *: see ?source clock/machine clock? for t mclk . 22.4.6 low-voltage detection ? normal mode (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, ec0, ec1, adtg 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns parameter symbol value unit remarks min typ max reset release voltage v pdl + 1.88 2.03 2.18 v at power supply rise reset detection voltage v pdl ? 1.8 1.93 2.06 v at power supply fall interrupt release voltage 0 v idl0 + 2.13 2.3 2.47 v at power supply rise interrupt detection voltage 0 v idl0 ? 2.05 2.2 2.35 v at power supply fall interrupt release voltage 1 v idl1 + 2.41 2.6 2.79 v at power supply rise interrupt detection voltage 1 v idl1 ? 2.33 2.5 2.67 v at power supply fall interrupt release voltage 2 v idl2 + 2.69 2.9 3.11 v at power supply rise interrupt detection voltage 2 v idl2 ? 2.61 2.8 2.99 v at power supply fall interrupt release voltage 3 v idl3 + 3.06 3.3 3.54 v at power supply rise interrupt detection voltage 3 v idl3 ? 2.98 3.2 3.42 v at power supply fall interrupt release voltage 4 v idl4 + 3.43 3.7 3.97 v at power supply rise interrupt detection voltage 4 v idl4 ? 3.35 3.6 3.85 v at power supply fall interrupt release voltage 5 v idl5 + 3.81 4.1 4.39 v at power supply rise interrupt detection voltage 5 v idl5 ? 3.73 4 4.27 v at power supply fall power supply start voltage v off ??1.6v power supply end voltage v on 4.39 ? ? v power supply voltage change time (at power supply rise) t r 697.5 ? ? s slope of power supply that the reset release signal generates within the rating (v pdl+ /v idl+ ) power supply voltage change time (at power supply fall) t f 697.5 ? ? s slope of power supply that the reset detection signal generates within the rating (v pdl- /v idl- ) reset release delay time t dp1 ??30s reset detection delay time t dp2 ??30s interrupt release delay time t di1 ??30s interrupt detect ion delay time t di2 ??30s interrupt threshold voltage transition stabilization time t stb ??30s int00 to int07, ec0, ec1, adtg 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
mb95710m series mb95770m series document number: 002-09307 rev. *d page 148 of 172 ? low power consumption mode (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) note: when being used for interrupt, the low-voltage detec tion circuit can be switched between normal mode and low power consumption mode. compared with normal mode, in low power consumption mode, while the detection voltage and release voltage are less accurate, and the de tection delay time and the release delay time become longer, there is less power consumption. for the diff erence in power consumption between normal mode and low power consumption mode, see ?22.3 dc characteristics?. for the method of switching between normal mode and low power consumption mode, refer to ?chapter 16 low-voltage detection circuit? in ?new 8fx mb95710m/770m series hardware manual?. parameter symbol value unit remarks min typ max interrupt release voltage 0 v idll0 + 2.06 2.3 2.54 v at power supply rise interrupt detection voltage 0 v idll0 ? 1.98 2.2 2.42 v at power supply fall interrupt release voltage 1 v idll1 + 2.33 2.6 2.87 v at power supply rise interrupt detection voltage 1 v idll1 ? 2.25 2.5 2.75 v at power supply fall interrupt release voltage 2 v idll2 + 2.6 2.9 3.2 v at power supply rise interrupt detection voltage 2 v idll2 ? 2.52 2.8 3.08 v at power supply fall interrupt release voltage 3 v idll3 + 2.96 3.3 3.64 v at power supply rise interrupt detection voltage 3 v idll3 ? 2.88 3.2 3.52 v at power supply fall interrupt release voltage 4 v idll4 + 3.32 3.7 4.08 v at power supply rise interrupt detection voltage 4 v idll4 ? 3.24 3.6 3.96 v at power supply fall interrupt release voltage 5 v idll5 + 3.68 4.1 4.52 v at power supply rise interrupt detection voltage 5 v idll5 ? 3.6 4 4.4 v at power supply fall power supply start voltage v offl ??1.6v power supply end voltage v onl 4.52 ? ? v power supply voltage change time (at power supply rise) t rl 7300 ? ? s slope of power supply that the interrupt release signal generates within the rating (v idll+ ) power supply voltage change time (at power supply fall) t fl 7300 ? ? s slope of power supply that the interrupt detection signal generates within the rating (v idll- ) interrupt release delay time t dil1 ??400s interrupt detect ion delay time t dil2 ??400s interrupt threshold voltage transition stabilization time t stbl ??400s interrupt low-voltage detection mode switch time t mdsw ??400s normal mode ? low power consumption mode
mb95710m series mb95770m series document number: 002-09307 rev. *d page 149 of 172 t dp2 /t di2 /t dil2 t dp1 /t di1 /t dil1 t r /t rl t f /t fl v cc v on /v onl v off /v offl v pdl+ /v idl+ v pdl- /v idl- time time internal reset signal or interrupt signal
mb95710m series mb95770m series document number: 002-09307 rev. *d page 150 of 172 22.4.7 i 2 c bus interface timing (v cc = 3.0 v to 5.5 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: the maximum t hd;dat in the standard-mode is applicab le only when the time during which the device is holding the scl signal at ?l? (t low ) does not extend. *3: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, provided that the condition of t su;dat 250 ns is fulfilled. parameter symbol pin name condition value unit standard- mode fast-mode min max min max scl clock frequency f scl scl r = 1.7 k , c = 50 pf* 1 01000400khz (repeated) start condition hold time sda scl t hd;sta scl, sda 4.0 ? 0.6 ? s scl clock ?l? width t low scl 4.7 ? 1.3 ? s scl clock ?h? width t high scl 4.0 ? 0.6 ? s (repeated) start condition setup time scl sda t su;sta scl, sda 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl, sda 0 3.45 *2 00.9 *3 s data setup time sda scl t su;dat scl, sda 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto scl, sda 4 ? 0.6 ? s bus free time between stop condition and start condition t buf scl, sda 4.7 ? 1.3 ? s sda scl t wakeup t hd;sta t su;dat f scl t hd;sta t su;sta t low t hd;dat t high t su;sto t buf
mb95710m series mb95770m series document number: 002-09307 rev. *d page 151 of 172 (v cc = 3.0 v to 5.5 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl r = 1.7 k , c = 50 pf* 1 (2 + nm/2)t mclk ? 20 ? ns master mode scl clock ?h? width t high scl (nm/2)t mclk ? 20 (nm/2)t mclk + 20 ns master mode start condition hold time t hd;sta scl, sda (-1 + nm/2)t mclk ? 20 (-1 + nm)t mclk + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl, sda (1 + nm/2)t mclk ? 20 (1 + nm/2)t mclk + 20 ns master mode start condition setup time t su;sta scl, sda (1 + nm/2)t mclk ? 20 (1 + nm/2)t mclk + 20 ns master mode bus free time between stop condition and start condition t buf scl, sda (2 nm + 4)t mclk ? 20 ? ns data hold time t hd;dat scl, sda 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl, sda (-2 + nm/2)t mclk ? 20 (-1 + nm/2)t mclk + 20 ns master mode it is assumed that ?l? of scl is not extended. the minimum value is applied to the first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl (nm/2)t mclk ? 20 (1 + nm/2)t mclk + 20 ns the minimum value is applied to the interrupt at the ninth scl . the maximum value is applied to the interrupt at the eighth scl . scl clock ?l? width t low scl 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl 4 t mclk ? 20 ? ns at reception
mb95710m series mb95770m series document number: 002-09307 rev. *d page 152 of 172 (v cc = 3.0 v to 5.5 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: r represents the pull-up resistance of the scl and sda lines, and c the load capacitance of the scl and sda lines. *2: ? see ?source clock/machine clock? for t mclk . ? m represents the cs[4:3] bits in the i 2 c clock control regi ster ch.0 (iccr0). ? n represents the cs[2:0] bits in the i 2 c clock control register ch.0 (iccr0). ? the actual timing of the i 2 c bus interface is determined by the val ues of m and n set by the machine clock (t mclk ) and the cs[4:0] bits in the iccr0 register. ? standard-mode: m and n can be set to values in the following range: 0.9 mhz < t mclk (machine clock) < 16.25 mhz. the usable frequencies of the machine clock are determ ined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 mhz < t mclk 10 mhz (m, n) = (8, 22) : 0.9 mhz < t mclk 16.25 mhz ? fast-mode: m and n can be set to values in the following range: 3.3 mhz < t mclk (machine clock) < 16.25 mhz. the usable frequencies of the machine clock are determ ined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22), (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 mhz < t mclk 10 mhz (m, n) = (5, 8) : 3.3 mhz < t mclk 16.25 mhz parameter symbol pin name condition value* 2 unit remarks min max start condition detection t hd;sta scl, sda r = 1.7 k , c = 50 pf* 1 2 t mclk ? 20 ? ns no start condition is detected when 1 t mclk is used at reception. stop condition detection t su;sto scl, sda 2 t mclk ? 20 ? ns no stop condition is detected when 1 t mclk is used at reception. restart condition detection condition t su;sta scl, sda 2 t mclk ? 20 ? ns no restart condition is detected when 1 t mclk is used at reception. bus free time t buf scl, sda 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl, sda 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl, sda t low ? 3 t mclk ? 20 ? ns at slave transmission mode data hold time t hd;dat scl, sda 0 ? ns at reception data setup time t su;dat scl, sda t mclk ? 20 ? ns at reception sda scl (with wakeup function in use) t wakeup scl, sda oscillation stabilization wait time + 2 t mclk ? 20 ?ns
mb95710m series mb95770m series document number: 002-09307 rev. *d page 153 of 172 22.4.8 uart/sio, serial i/o timing (v cc = 3.0 v to 5.5 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc uck0, uck1, uck2 internal clock operation output pin: c l = 80 pf + 1 ttl 4 t mclk *? ns uck uo time t slov uck0, uck1, uck2, uo0, uo1, uo2 ? 190 + 190 ns valid ui uck t ivsh uck0, uck1, uck2, ui0, ui1, ui2 2 t mclk *? ns uck valid ui hold time t shix uck0, uck1, uck2, ui0, ui1, ui2 2 t mclk *? ns serial clock ?h? pulse width t shsl uck0, uck1, uck2 external clock operation output pin: c l = 80 pf + 1 ttl 4 t mclk *? ns serial clock ?l? pulse width t slsh uck0, uck1, uck2 4 t mclk *? ns uck uo time t slov uck0, uck1, uck2, uo0, uo1, uo2 ?190ns valid ui uck t ivsh uck0, uck1, uck2, ui0, ui1, ui2 2 t mclk *? ns uck valid ui hold time t shix uck0, uck1, uck2, ui0, ui1, ui2 2 t mclk *? ns 0.2 v cc 0.2 v cc 0.8 v cc t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0, uck1, uck2 uo0, uo1, uo2 ui0, ui1, ui2 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode
mb95710m series mb95770m series document number: 002-09307 rev. *d page 154 of 172 22.4.9 comparator timing (av cc = 1.8 v to 5.5 v, av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter pin name value unit remarks min typ max voltage range cmp0_p, cmp0_n 0?av cc v offset voltage cmp0_p, cmp0_n ? 20 ? + 20 mv delay time cmp0_o ? 600 1200 ns overdrive 5 mv ? 120 420 ns overdrive 50 mv power down delay cmp0_o ? ? 1200 ns power down recovery pd: 1 0 0?150ns power down pd: 0 1 power up stabilization time cmp0_o ? ? 1200 ns output stabilization time at power up bandgap reference voltage ? 1.15 1.21 1.27 v t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0, uck1, uck2 uo0, uo1, uo2 ui0, ui1, ui2 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slsh t shsl ? external shift clock mode
mb95710m series mb95770m series document number: 002-09307 rev. *d page 155 of 172 22.5 a/d converter 22.5.1 a/d converter electrical characteristics (av cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *: see ?notes on using a/d converter? fo r details of the minimum sampling time. parameter symbol value unit remarks min typ max resolution ? ??12bit to t a l e r r o r ? 6? + 6lsbv cc 2.7 v ? 10 ? + 10 lsb v cc < 2.7 v linearity error ? 3? + 3lsbv cc 2.7 v ? 5? + 5lsbv cc < 2.7 v differential linearity error ? 1.9 ? + 1.9 lsb v cc 2.7 v ? 2.9 ? + 2.9 lsb v cc < 2.7 v zero transition voltage v 0t v ss ? 6 lsb ? v ss + 8.2 lsb v full-scale transition voltage v fst av cc ? 6.2 lsb ? av cc + 9.2 lsb v sampling time t s *?10s compare time t cck 0.861 ? 14 s v cc 2.7 v 2.8 ? 14 s v cc < 2.7 v time for transiting to operation enabled state t stt 1??s analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain v ss ?av cc v
mb95710m series mb95770m series document number: 002-09307 rev. *d page 156 of 172 22.5.2 notes on using a/d converter ? external impedance of analog input and its sampling time the a/d converter of the mb95710m/770m series has a sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting a/d conversion pr ecision. therefore, to satisfy the a/d conversion precision standard, considering the relationshi p between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. in addition, if sufficient sampling time cannot be secured, con nect a capacitor of about 0.1 f to the analog input pin. ? relationship between external impedance and minimum sampling time the necessary sampling time varies according to external impedance. ensure that the following conditions are ful- filled when setting the sampling time. t s : sampling time rin : input resistance of a/d converter cin : input capacitance of a/d converter rext : output impedance of external circuit ? a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. note: the values are reference values. 4.5 v v cc 5.5 v 2.7 v v cc < 4.5 v 0.9 k (max) 1.6 k (max) 13 pf (max) v cc rin cin 13 pf (max) 1.8 v v cc < 2.7 v 4.0 k (max) 13 pf (max) comparator analog input pins (an00 to an07) analog signal source rin cin rext ? analog input equivalent circuit ts rin rext + () cin 9
mb95710m series mb95770m series document number: 002-09307 rev. *d page 157 of 172 22.5.3 definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 12, analog voltage can be divided into 2 12 = 4096. ? linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?000000000000? ?000000000001?) of a device to the full-sc ale transition point (?111111111111? ?111111111110?) of the same device. ? differential linear error (unit: lsb) it indicates how much the input voltage required to change the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a th eoretical value. the error ca n be caused by a zero tran- sition error, a full-scale transition errors, a linearity error, a quantum error, or noise. v fst ideal i/o characteristics 0x001 0x002 0x003 0x004 0xffd 0xffe 0xfff digital output digital output 2 lsb v 0t 1 lsb 0.5 lsb total error analog input analog input 0x001 0x002 0x003 0x004 0xffd 0xffe 0xfff actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n ? 1) to 0xn {1 lsb (n ? 1) + 0.5 lsb} v nt total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb lsb = v cc ? v ss 4096 v 1 lsb = v ss v cc v ss v cc
mb95710m series mb95770m series document number: 002-09307 rev. *d page 158 of 172 zero transition error linearity error full-scale transition error 0x001 0x002 0x003 0x004 0xffd 0xffe 0xfff digital output differential linearity error of digital output n v (n + 1)t ? v nt 1 lsb ? 1 = linearity error of digital output n v nt ? {1 lsb n + v 0t } 1 lsb = digital output analog input 0x001 0x002 0xffc 0xffd 0x003 0xffe 0xfff 0x004 actual conversion characteristic actual conversion characteristic v 0t (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) v ss v cc v ss v cc v ss v cc v ss v cc analog input digital output analog input ideal characteristic {1 lsb n + v 0t } actual conversion characteristic ideal characteristic actual conversion characteristic v 0t (measurement value) v fst (measurement value) v nt differential linearity error 0x(n-2) 0x(n-1) 0xn 0x(n+1) digital output analog input actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n + 1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n ? 1) to 0xn v 0t (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc ? 2 lsb [v] ideal characteristic
mb95710m series mb95770m series document number: 002-09307 rev. *d page 159 of 172 22.6 flash memory program/erase characteristics *1: v cc = 5.5 v, t a = + 25 c, 0 cycle *2: v cc = 1.8 v, t a = + 85 c, 100000 cycles *3: these values were converted from the result of a techno logy reliability assessment. (t hese values were converted from the result of a high temperature accelerated test us ing the arrhenius equation with the average temperature being + 85 c.) parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.3* 1 1.6* 2 s the time of writing ?0x00? prior to erasure is excluded. sector erase time (24 kbyte sector and 32 kbyte sector) ?0.6* 1 3.1* 2 s the time of writing ?0x00? prior to erasure is excluded. byte writing time ? 17 272 s system-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 1.8 ? 5.5 v flash memory data retention time 20* 3 ?? year average t a = + 85 c number of program/erase cycles: 1000 or below 10* 3 ?? average t a = + 85 c number of program/erase cycles: 1001 to 10000 inclusive 5* 3 ?? average t a = + 85 c number of program/erase cycles: 10001 or above
mb95710m series mb95770m series document number: 002-09307 rev. *d page 160 of 172 23. sample characteristics ? power supply current temp erature characteristics 0 20 60 40 140 120 100 80 1234567 i ccl [ a] v cc [v] i ccl ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) subclock mode with the external clock operating 0 2 6 4 10 8 1234567 i cc [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i cc ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating 0 2 6 4 10 8 i cc [ma] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz ? 50 0 + 50 + 100 + 150 t a [ c] 0 1 3 2 4 1234567 i ccs [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 1 2 4 3 i ccs [ma] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz ? 50 0 + 50 + 100 + 150 t a [ c] 0 20 40 140 120 100 80 60 i ccl [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cc ? t a v cc = 3.3 v, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the ex ternal clock operating i ccs ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccs ? t a v cc = 3.3 v, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccl ? t a v cc = 3.3 v, f mpl = 16 khz (divided by 2) subclock mode with the external clock operating
mb95710m series mb95770m series document number: 002-09307 rev. *d page 161 of 172 0 1 2 5 4 3 i cct [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cct ? t a v cc = 3.3 v, f mpl = 16 khz (divided by 2) watch mode with the external clock operating 0 2 5 10 9 8 7 6 1 3 4 i ccls [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i ccls ? t a v cc = 3.3 v, f mpl = 16 khz (divided by 2) subsleep mode with the external clock operating 0 2 1 5 4 3 10 9 8 7 6 1234567 i ccls [ a] v cc [v] 0 1 3 2 5 4 1234567 i cct [ a] v cc [v] 0 200 100 400 300 600 500 1234567 i ccts [ a] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 100 300 200 600 500 400 i ccts [ a] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz ? 50 0 + 50 + 100 + 150 t a [ c] i ccls ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) subsleep mode with the external clock operating i cct ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) watch mode with the external clock operating i ccts ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating i ccts ? t a v cc = 3.3 v, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating
mb95710m series mb95770m series document number: 002-09307 rev. *d page 162 of 172 0 1 2 5 4 3 i cch [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cch ? t a v cc = 3.3 v, f mpl = (stop) substop mode with the external clock stopping 0 1 3 2 5 4 1234567 i cch [ a] v cc [v] 0 1 3 2 5 4 1234567 i ccmcr [ma] v cc [v] 0 1 2 5 4 3 i ccmcr [ma] ? 50 0 + 50 + 100 + 150 t a [ c] 0 2 6 4 10 8 1234567 i ccmcrpll [ma] v cc [v] 0 2 4 10 8 6 i ccmcrpll [ma] ? 50 0 + 50 + 100 + 150 t a [ c] i cch ? v cc t a = + 25 c, f mpl = (stop) substop mode with the external clock stopping i ccmcr ? v cc t a = + 25 c, f mp = 4 mhz (no division) main cr clock mode i ccmcr ? t a v cc = 3.3 v, f mp = 4 mhz (no division) main cr clock mode i ccmcrpll ? v cc t a = + 25 c, f mp = 16 mhz (pll multiplication rate: 4) main cr pll clock mode i ccmcrpll ? t a v cc = 3.3 v, f mp = 16 mhz (pll multiplication rate: 4) main cr pll clock mode
mb95710m series mb95770m series document number: 002-09307 rev. *d page 163 of 172 (continued) 0 50 200 150 100 i ccscr [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i ccscr ? t a v cc = 3.3 v, f mpl = 50 khz (divided by 2) sub-cr clock mode 0 100 50 200 150 1234567 i ccscr [ a] v cc [v] i ccscr ? v cc t a = + 25 c, f mpl = 50 khz (divided by 2) sub-cr clock mode 0 2 6 4 10 8 1234567 i ccmpll [ma] v cc [v] 0 2 4 10 8 6 i ccmpll [ma] ? 50 0 + 50 + 100 + 150 t a [ c] i ccmpll ? v cc t a = + 25 c, f mp = 16 mhz (pll multiplication rate: 4) main pll clock mode i ccmpll ? t a v cc = 3.3 v, f mp = 16 mhz (pll multiplication rate: 4) main pll clock mode 0 2 6 4 10 8 1234567 i a [ma] av cc [v] i a ? av cc t a = + 25 c, f mp = 16 mhz (divided by 2) main clock mode with the external clock operating 0 2 4 10 8 6 i a [ma] ? 50 0 + 50 + 100 + 150 t a [ c] i a ? t a v cc = 3.3 v, f mp = 16 mhz (divided by 2) main clock mode with the ex ternal clock operating
mb95710m series mb95770m series document number: 002-09307 rev. *d page 164 of 172 ? input voltage characteristics 0 1 2 4 5 1 3456 2 v ihi /v ili [v] v cc [v] 3 v ihi v ili v ihi ? v cc and v ili ? v cc t a = + 25 c 0 1 2 4 5 1 3456 2 v ihs /v ils [v] v cc [v] 3 v ihs v ils 0 1 2 4 5 1 3456 2 v ihm /v ilm [v] v cc [v] 3 v ihm v ilm v ihs ? v cc and v ils ? v cc t a = + 25 c v ihm ? v cc and v ilm ? v cc t a = + 25 c
mb95710m series mb95770m series document number: 002-09307 rev. *d page 165 of 172 ? output voltage characteristics 0.0 0.2 0.4 0.8 1.0 02 13579 4 6 8 101112131415 v ol [v] i ol [ma] 0.6 v cc = 2.0 v v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v v cc = 4.0 v v cc = 1.8 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v ol ? i ol t a = + 25 c 0.0 0.2 0.4 0.8 1.0 0 ? 2 ? 1 ? 3 ? 5 ? 7 ? 9 ? 4 ? 6 ? 8 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 v cc ? v oh [v] i oh [ma] 0.6 v cc = 2.0 v v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v v cc = 4.0 v v cc = 1.8 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh ) ? i oh t a = + 25 c
mb95710m series mb95770m series document number: 002-09307 rev. *d page 166 of 172 ? pull-up characteristics 24. mask options no. part number mb95f714j mb95f716j mb95f718j mb95f774j mb95f776j mb95f778j mb95f714m mb95f716m mb95f718m mb95f774m mb95f776m mb95f778m selectable/fixed fixed 1 low-voltage detection reset with low-voltage detection reset wit hout low-voltage detection reset 2 reset without dedicated reset input with dedicated reset input 0 50 100 150 300 250 200 2 1 3456 r pull [k ] v cc [v] r pull ? v cc t a = + 25 c
mb95710m series mb95770m series document number: 002-09307 rev. *d page 167 of 172 25. ordering information part number package mb95f714jpmc-g-sne2 mb95f714mpmc-g-sne2 mb95f716jpmc-g-sne2 MB95F716MPMC-G-SNE2 mb95f718jpmc-g-une2 mb95f718mpmc-g-sne2 80-pin plastic lqfp (lqh080) mb95f774jpmc1-g-sne2 mb95f774mpmc1-g-sne2 mb95f776jpmc1-g-sne2 mb95f776mpmc1-g-sne2 mb95f778jpmc1-g-sne2 mb95f778mpmc1-g-sne2 64-pin plastic lqfp (lqd064) mb95f774jpmc2-g-sne2 mb95f774mpmc2-g-sne2 mb95f776jpmc2-g-sne2 mb95f776mpmc2-g-sne2 mb95f778jpmc2-g-une2 mb95f778mpmc2-g-sne2 64-pin plastic lqfp (lqg064)
mb95710m series mb95770m series document number: 002-09307 rev. *d page 168 of 172 26. package dimension package type package code lqfp 80 lqh 080 %*.&/4*0/4 .*/ /0. ."9 " " c d %#4$ % #4$ f #4$ & & - - #4$ #4$ 4:.#0- #0550. 7*&8 " " % % f c % $ "# % $ "# % $ "# % & & c 4&$5*0/ "" d 4&"5*/( 1-"/& $ " " - - 4*%& 7*&8 501 7*&8 1"$,"(&065-*/& -&"%-2'1 99 ..-2) 3fw 002-11501 **
mb95710m series mb95770m series document number: 002-09307 rev. *d page 169 of 172 package type package code lqfp 64 lqd 064 %*.&/4*0/4 4:.#0- .*/ /0. ."9 " " c d %#4$ % #4$ f#4$ & & - - #4$ #4$ % % f & & $ "# % c $ "# % $ "# % " " c 4&$5*0/ "" d - - " " 4&"5*/( 1-"/& $ 4*%& 7*&8 501 7*&8 #0550. 7*&8 1"$,"(&065-*/& -&"%-2'1 99 .. -2% 3fw 002-11499 **
mb95710m series mb95770m series document number: 002-09307 rev. *d page 170 of 172 package type package code lqfp 64 lqg 064 %*.&/4*0/ 4:.#0- .*/ /0. ."9 " " c d % #4$ % #4$ f #4$ & & - - #4$ #4$ ? ? % % f & & $ "# % c $ "# % $ "# % $ " " 4&"5* /( 1-" /& c 4&$5*0/" " d " " - - 4*%& 7*&8 501 7*&8 #0550. 7*&8 99.. -2( 3&7 1"$,"(&065-*/& -&"%-2'1 002-13881 **
mb95710m series mb95770m series document number: 002-09307 rev. *d page 171 of 172 document history page document title: mb95710m series, mb95770m series, new 8fx 8-bit microcontrollers document number: 002-09307 revision ecn orig. of change submission date description of change ** - yska 07/31/2013 migrated spansion ds702-00019-1v0- e to cypress and assigned document number 002-09307. no change to document contents or format. *a 5511943 yska 11/08/2016 updated to cypress template *b 5633448 hter 03/07/2017 changed the package codes as the following from ?fpt-80p-m37? to ?lqh080? from ?fpt-64p-m38? to ?lqd064? from ?fpt-64p-m39? to ?lqg064? in chapter: 1.product line-up (page 6, 9) 2.packages and corresponding products (page 9) 4.pin assignment (page 11 to 12) 25.ordering information (page 167) 26.package dimensions (page 168 to 170). changed the part numbers from ?mb95f778jpmc2 -g-sne2? to ?mb95f778jpmc2-g-une2? in chapter 25.ordering information (page 167). *c 5772061 ysat 06/15/2017 adapted new cypress logo *d 5900838 hual 09/29/2017 modified from ?mb95f718jpmc-g- sne2? to ?mb95f718jpmc-g-une2? in 25.ordering information (page 167).
document number: 002-09307 rev. *d revised september 29, 2017 page 172 of 172 mb95710m series mb95770m series all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semiconductor corporation, 2013-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desig n, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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